Abstract: A novel method and apparatus of detecting unique items as they are inserted into a product packaging system that is easily adaptable to current product packaging and prize insertion systems. A number of different types of sensors may be used in conjunction with the insertion device to detect the unique prize before it is inserted into a product packaging system. The sensor used will vary depending on the particular application. Sensors that may be used include a capacitive proximity sensor, a thickness sensor, a reflectivity sensor, a transmissivity sensor, a stiffness sensor, a color sensor, or even an odor or chemical sensor. Ideally, the type sensor used will detect a feature of the unique item that is easily distinguishable from other items being inserted. Once the sensor detects the prize and generates a signal, this signal can be used to perform a variety of useful functions.

Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.

Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.

Abstract: An interrupt handling mechanism within a data processing system is used to assign interrupts among multiple interrupt presentation controllers while avoiding the use of a significant amount of signal lines. An interrupt input message from an interrupt source controller is input into an interrupt presentation controller. Fields are added to the interrupt input message to facilitate the assignment of the interrupt input message to an interrupt presentation controller. The input interrupt message is passed between the interrupt presentation controller in a sequential fashion such that the collection of controllers forms a logical ring. On the first circle of the ring, the priority of the processors capable of handling the interrupt is discovered. A second pass through the interrupt presentation controller is used to assign the first processor that is both capable of taking the interrupt and also has an equal or lower priority to that noted on the first pass as to best priority.