Abstract: A method for serializing access to computer system resources without disabling interrupts in critical code sections or requiring excessive use of spin locks. A queue lock is introduced that allows an interrupt process to enqueue and be processed in turn without a spin lock and to block process code access to a particular resource until all interrupts are processed. Process level code is blocked from accessing a locked resource while requests for accesses from interrupt level code are queued in a deferred work queue which is processed prior to the release of the blocking lock. Establishment of deferred work queue means that processing can continue without disablement of interrupts and without significant overhead consumed by processes holding spin locks.
Type:
Grant
Filed:
March 31, 1992
Date of Patent:
December 28, 1993
Assignee:
International Business Machines Corporation
Inventors:
Larry B. Brenner, Barry P. Lubart, Jeffrey S. Lucash, John C. Rathjen, Jr., Ronald Sasala, Thomas Van Weaver
Abstract: An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.
Type:
Grant
Filed:
May 16, 1989
Date of Patent:
November 12, 1991
Assignee:
International Business Machines Corporation
Inventors:
Satish Gupta, Randall L. Henderson, Nathan R. Hiltebeitel, Robert Tamlyn, Steven W. Tomashot, Todd Williams