Abstract: A record and playback system for video images, especially suited for multi-camera industrial surveillance. Techniques for acquiring multiple asynchronous camera inputs, compressing video images, and storing digital image data are described. Selective resolution recording improves object discernability without large large increase in data storage. A recording system with automatic data archive that eliminates the need for regular operator attention is disclosed.

Abstract: A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a similar way: the low-order bits are computed with a conventional carry save adder (CSA) followed by a carry propagate adder (CPA), while the high-order bits are computed with an incrementer and selection logic. The first and second circuits are combined to form a third arithmetic circuit that takes four input operands, the first of which is wider than the other three, and speculatively computes two results: (1) the sum of the first and second input operands; and (2) the sum of the first, third, and fourth input operands. This combined circuit contains all of the elements of the first two circuits, but shares a single incrementer. A degenerate case of the third circuit occurs when the second and third inputs are common.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a similar way: the low-order bits are computed with a conventional carry save adder (CSA) followed by a carry propagate adder (CPA), while the high-order bits are computed with an incrementer and selection logic. The first and second circuits are combined to form a third arithmetic circuit that takes four input operands, the first of which is wider than the other three, and speculatively computes two results: (1) the sum of the first and second input operands; and (2) the sum of the first, third, and fourth input operands. This combined circuit contains all of the elements of the first two circuits, but shares a single incrementer. A degenerate case of the third circuit occurs when the second and third inputs are common.

Abstract: A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or a zero. The three-input comparator can be modified to be a three-input adder by using a full carry-propagate adder (CPA). By taking into account a priori restrictions on the possible input operands, these arithmetic circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.