Patents Represented by Attorney W. Eric Boyd
  • Patent number: 7440449
    Abstract: A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: October 21, 2008
    Assignee: Irvine Sensors Corp.
    Inventors: John C. Carson, Volkan H. Ozguz
  • Patent number: 7335576
    Abstract: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: February 26, 2008
    Assignee: Irvine Sensors Corp.
    Inventors: Ludwig David, James Yamaguchi, Stuart Clark, W. Eric Boyd
  • Patent number: 6998328
    Abstract: A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. Recesses are formed on a substrate and a dielectric layer with conductive pads is created for the receiving of one or more die. Die are flip-chip bonded to the conductive pads and all voids under-filled. The neo-wafer is thinned to expose the dielectric and the conductive pads exposed, creating a neo-wafer.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: February 14, 2006
    Assignee: Irvine Sensors Corp.
    Inventor: Jonathan Michael Stern
  • Patent number: 6993835
    Abstract: A method for electrical interconnection of angularly disposed and abutted conductive patterns is disclosed along with a device created from the method. Conventional wire bonding equipment is used to apply a conductive metal ball at the junction of angularly disposed conductive patterns by orienting a cornerbond assembly whereby one or more conductive metal balls are orthogonally applied and electrically connected to the respective conductive patterns.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: February 7, 2006
    Assignee: Irvine Sensors Corp.
    Inventor: Douglas Marice Albert