Abstract: Method and apparatus for auto-negotiation of a programmable logic device for any of a plurality of communication protocols is described. The programmable logic device is programmed for auto negotiation to establish a communication session. The programmable logic device has access to transceiver attributes. A portion of the transceiver attributes are selected in response to session information from the auto negotiation. The portion of the transceiver attributes selected are for configuring at least one transceiver for a communication protocol.

Abstract: Method and apparatus for data transfer validation is described. Configuration data is obtained. A signature for the configuration data is generated. The configuration data and the signature are stored in a first memory. The configuration data is transferred to a second memory for storage. The configuration data transferred is read to generate another signature, where the other signature is for the configuration data transferred. The configuration data read is compressed to provide the other signature. The signature is transferred for comparison with the other signature to validate whether the configuration data transferred was transferred without error. The method and apparatus may be used when transferring configuration data, including, but not limited to, transfer of configuration data from a memory to a programmable logic device.

Abstract: Method and apparatus for a bi-direction interface and communication link are described. More particularly, an input/output block is formed with a digitally controlled impedance output driver output coupled at an input/output node to an input terminal of a differential amplifier. Another terminal of the differential amplifier is used for inputting a reference voltage. As the digitally controlled impedance output buffer may be adjusted for impedance matching with transmission line impedance, no parallel terminating resistance is needed. Accordingly, two such input/output blocks may be coupled to form a bi-directional communication link with the advantage of an absence of parallel termination resistance at inputs to such input/output blocks.

Abstract: A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Abstract: Method and apparatus for configuring a programmable logic device using configuration data stored in an external memory is described. In an example, a boundary scan port includes a data input terminal and a data output terminal. An instruction-set processor includes a first interface coupled to the boundary scan port and a second interface coupled to a configuration memory within the programmable logic device. The data output terminal of the boundary scan port is coupled to provide instruction data to the external memory and the data input terminal is coupled to receive configuration data from the external memory in response to the instruction data. The instruction-set processor is configured to provide configuration data to the configuration memory.

Abstract: A oscillator controller (1300, 1500) is described. Differential logic receives a clock signal and an inverted version thereof (210, 210B) and an oscillator signal and an inverted version thereof (208, 208B), where the clock signal (210) and the oscillator signal (208) having different frequencies. The differential logic provides a differential output (1611, 1612) at least partially responsive to at least one of the clock signal and the oscillator signal. The differential logic is a combinational circuit in an oscillator alignment state and a sequential circuit in a hard-phase alignment state. Control signals (1317, 1318) are used in part to selectively alternate between putting the differential logic in the oscillator alignment state and in the hard-phase alignment state.

Abstract: Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.

Abstract: Method and apparatus for a nonlinear current circuit element are described, and method and apparatus using the nonlinear current circuit element in current-source self-biasing circuits are described. In one embodiment, a transistor is provided having source and drain terminals coupled together. This transistor has a significant gate tunneling current used beneficially to provide a nonlinear current circuit element. This nonlinear current circuit element is used in a plurality of current-source self-biasing circuits.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal having a first frequency. A dedicated logic circuit embedded within the programmable logic device is operable using a second clock signal synchronized with the first clock signal and having a second frequency, the second frequency being a multiple of the first frequency. An interface coupled between one or more of the programmable logic blocks and the dedicated logic circuit includes multiplexer circuitry to multiplex output signals produced by the one or more programmable logic blocks among input terminals of the dedicated logic circuit.

Abstract: Method and apparatus for automatically eliminating inferred latches created by hardware design language (HDL) source code is described. A node tree is built from the HDL source code based on the HDL's Language Reference Manual. The node tree is scanned to identify one or more conditional logic constructs that are sources for creation of inferred latches. A modified node tree is generated by automatically adding and/or modifying sub-productions of the conditional language constructs that create the inferred latches.

Abstract: Apparatus for network and system on a single programmable logic device is described. The programmable logic includes port modules. The port modules have configurable logic configured to process communications for routing communications. The port modules are configured to the process communications for at least one of a plurality of protocols.

Abstract: Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to the test pattern. State data responsive to the test pattern is obtained. The state data may be obtained from a readback datastream generated by the PLD. The expected state data may be generated by a second PLD that is known to contain no faults. The state data is compared with expected state data to produce difference information. The difference information is used, or more particularly is iteratively generated, to localize a fault or faults within a unit under test.

Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.

Abstract: Method and apparatus for determining power dissipation for an integrated circuit using computer simulation is described. More particularly, the integrated circuit is divided into cells, and one or more nodes are identified within each of the cells. A capacitive load value is ascribed to each of the nodes, and code is generated to track charges in state of each of the nodes. A total for changes in state for each node is divided by simulation time to determine a switching frequency. Using switching frequency, capacitive load and source voltage, dynamic power dissipation for each node may be determined. By summing dynamic power dissipation for all said nodes, total dynamic power dissipation may be determined.

Abstract: Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.

Abstract: Method and apparatus for thermally conditioning a microchip is described. The microchip (104) is thermally conditioned responsive to a temperature target over an interval of time. A diode voltage of a diode (503) of the microchip (104) is measured from which diode temperature is determined. The diode temperature is compared with the temperature target to determine a temperature error. This thermal conditioning may be repeated, where interval times are adjustable responsive to temperature error, until a stabilization band (401) is reached. Because a diode (503) of the microchip (104) is used, junction temperature, as opposed to external surface temperature of the microchip package, is obtained. Accordingly, a thermocouple attached to the external surface of the microchip is not needed.

Abstract: A pulse-width controller (1800) is described. Pulse generators (1700L, 1700H) are coupled to receive clock signals (1320, 1321) and configured to extend respective high-time and low-time pulse widths to provide signals with lengthened pulse widths (1320P, 1321P). Control signals (1803, 1804) are generated from pulse-width lengthened signals (1320P, 1321P). Clock signals (1320, 1321) and the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are provided to differential logic (1823 through 1828), such as Differential Cascode Voltage Switch Logic, to provide a differential output (1611, 1612) which is duty-cycle adjusted. The control signals (1803, 1804) in combination with the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are used to selectively activate a respective portion of the differential logic (1823 through 1828) to pass signals to the differential output (1611, 1612).

Abstract: Method for configuring a routing program for routing connections between an integrated circuit device and an embedded core is described. More particularly, horizontal and a vertical pitch are obtained for the integrated circuit device and the embedded core. A horizontal or a vertical pitch is selected from the embedded core to define pitch for the integrated circuit device to accommodate difference in pitch between the two. Additionally, an integrated circuit having interconnect layers using this compromise pitch are described.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.