Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath is configured to operate at two frequencies to accommodate the programmable circuitry in the integrated circuit.

Abstract: Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.

Abstract: A programmable device with contact via programming to reduce leakage current and a method for reducing standby power for such programmable device are described. Configuration memory cells are identified responsive to instantiation of a user design in a test platform of the programmable device. The programmable device is via programmed during manufacturing thereof to not couple for programmability a first portion of the configuration memory cells and to form a first portion of the user design associated with the first portion of the configuration memory cells as hard-wired and to couple for programmability a second portion of the configuration memory cells for subsequent instantiation of a second portion of the user design in the programmable device.

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract: Circuit placement for increasing circuit packing density for an integrated circuit is described. A design is synthesized and mapped. Components of the design are placed to provide a first placed design. A congestion density map is generated for the first placed design. A congestion region in the congestion density map is identified and targeted for determining if the first placed design has a control set conflict. A first circuit object associated with the control set conflict is selected and either re-placed or re-synthesized to at least diminish the control set conflict.

Abstract: A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit.

Abstract: Data recovery, as well as associated circuitry and system, is described. An input word stream having a word width of at least one word is obtained and a sliding window is applied to it to resolve phases. Scores for phases are determined at least in part by: subdividing the sliding window into sample portions; applying a homogeneity function to each of the sample portions to determine respective values therefor; and summing sets of the values respectively associated with the phases to provide the scores. A score is selected from the scores according to at least one criterion to select a phase from the phases. A portion of a delayed version of the input word stream is sampled by application of the sliding window thereto using the phase selected to output sampled bits.

Abstract: Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.

Abstract: A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PD design to the columnar ASIC-like design.

Abstract: An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.

Abstract: A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.

Abstract: Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.

Abstract: A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponents as between corresponding first adjusted values. A first operation specific floating-point processing unit (OFPU) is coupled to receive the first adjusted values and includes first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results. The first numerical results are not normalized prior to a second floating-point operation.

Abstract: A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.

Abstract: A direct memory access engine is described. The direct memory access engine has a transmit channel coupled to a transmit interface, a receive channel coupled to a receive interface, an arbiter coupled to both the transmit channel and the receive channel, and a set of queues coupled to the arbiter. The set of queues has command buffers, transmit buffers, and receive buffers. A direct memory access-to-processor bus interface is coupled to the set of queues. The transmit buffers are for first separate read and write requests. The receive buffers are for second separate read and write requests which are independent of the first separate read and write requests.

Abstract: A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: Multiplexing data from bitstreams is described. Data status is determined for data of each of the bitstreams. Stream numbers are assigned respectively to the bitstreams, and the data of each of the bitstreams is controllably stored in respective memory. A memory buffer of the memory buffers is controllably selected. The data obtained from the memory buffer selected is parsed to provide an output. The controllably selecting and the parsing are repeated to obtain and parse the data stored in at least one other memory buffer of the memory buffers to provide the output. The output is multiplexed data from the bitstreams respectively associated with the memory buffer and the at least one other memory buffer.

Abstract: A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.

Abstract: A method for decoding, including: obtaining an op-code from a master device; setting a mode to mask a first portion of the bits of the op-code, where the first portion of the bits are for being treated as a wildcard value; and decoding a second portion of the op-code that is not masked to determine whether the op-code is for a slave device. The decoding of the second portion is performed by a controller having a decoder, and the controller bridges the master device for communication with the slave device. The decoding of the first portion of the bits is performed by the slave device. The first portion of the bits identifies an instruction from a group of instructions, and the group of instructions uses a single configuration register of registers of the controller.