Abstract: A signal processing system that has an improved modular architecture so that a selected number of arithmetic element (AE) units may be utilized with a single arithmetic element controller (AEC) unit to provide a system that can be readily expanded or decreased on computational ability. All of the AE units perform similar calculations under control of the AEC unit in response to common address control and coefficient signals. Each AE unit has its own extended work store (EWS) unit with all of the EWS units responding to the same address and control signals, from either the AEC unit or an external interface unit to conform to the modular architecture. Each EWS unit is synchronized with the AE unit, thus allowing continuous and high speed computations to be performed. Also, each of the EWS units is coupled to the external interface unit for receiving and transferring data when not being accessed by the AEC unit.

Abstract: A false alarm control processor that receives sampled input radar video data and provides an output signal having a zero mean value. The processor accumulates the sample video for a range sweep of range bins, then stores the value and resets a counter. The stored value is scaled to form an estimate of the mean and subtracted from the input video signals of the following sweep. To prevent the mean from being biased by strong targets, a target exclusion function may be included to prevent accumulation of video from strong targets. However, if the noise or jamming level has increased for more range bins than a target would occupy, the video is then sampled by the accumulator so that the mean is responsive to changes in the level of the noise. Thus, the system provides a constant false alarm rate and accurate azimuth estimation in the azimuth integrator filter as well as allowing the azimuth integrator to operate with a relatively small dynamic range.

Abstract: An automatic level and gain control system operable with a sensor to match the dynamic range of the display or other processing elements to the signal provided by the sensor for developing an image with improved dynamic range utilization (or contrast). Peak detection is provided with a conditional integrator so that the effect of high level narrow peaks is substantially suppressed. This system rapidly reaches and maintains a condition of providing the video signal to the display (or other processing) at a desired voltage level and over a desired dynamic range to continually maintain an image having optimum contrast within the dynamic range limitations of the processor or display system.

Abstract: A window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal. Several latch networks are disclosed for both single and dual differential input configurations. The dual input configuration includes first and second pairs of differential transistors which are coupled to a differential regenerative and latching pair of transistors. The regenerative and latching transistor pair provides an output signal having first or second states only upon the required clock signal being applied to a current switching transistor pair. Negative differential signals applied to both first and second pairs of differential transistors results in a "0" logic state output signal from the regenerative and latching transistors. A positive differential signal results in a logic "1" output state. Positive input signals applied to both differential transistors results in a logic "0" output state.

Abstract: A charge coupled device (CCD) transversal filter (TVF) having an improved electrode configuration and connecting arrangement which minimizes the noise that is added to the signal to provide a relatively high amplitude output signal and a relatively high output signal-to-noise ratio. The CCD transversal filter operates with the weighting coefficients determined by the one sided width of the electrodes and with one end of the split electrodes coupled to the output and the other ends of the split electrodes coupled to a reference voltage source. When some of the weighting coefficients of the desired impulse response are negative the output ends of the weighting electrodes are selectively connected to either the inverting or noninverting common connections of a differential amplifier in turn providing the transversal filter output signals. For a single polarity impulse response, all of the electrodes are coupled to an output arrangement without requiring an inversion.

Abstract: A quantizer network is disclosed for decoding an analog signal and providing a four-bit digital output. The analog input signal is divided or quantized into sixteen discrete voltage ranges and applied to sixteen differential amplifiers. Each amplifier has a different reference which must be exceeded before it provides an output signal. The sixteen differential amplifiers are connected to nine latch networks which respond to the signals from the amplifiers and provide a cyclic code in response thereto. The latch networks are connected to a network of logic gates which decode the cycle code into a four-bit digital output signal. The output signals from the logic gate network are applied to output stages which extend the valid time of the output signal from the logic gates.

Abstract: A CTD (charge transfer device) transversal filter that utilizes displacement current charge substraction techniques to create positive displacement current charge summation for some electrodes and negative displacement current charge summation for other electrodes into and out of a common electrode node. The operation is accomplished by shifting by one half bit all signal charges within the negative tap structure with respect to the signal charges within the positive tap structure. Thus, only a single summing capacitance node is utilized with all taps, plus and minus, being connected together, eliminating the differential amplifier requirement of other CTD transversal filters. An arrangement of either zero tap weights with an extra one bit delay or a separate high-frequency pulse eliminating a one bit delay are utilized to provide or not provide, as desired, zero weighting between the tap sections.

Abstract: An automatic clutter detecting and mapping system in which the area being mapped is broken up into clutter mapping quantum areas with corresponding storage cells including reject codes for automatically rejecting clutter returns which may occur in intermittent or fading clutter occurring a small percentage of the time for example. For each clutter mapping cell a clutter count and a reject code are stored in a main memory and in a first mode which is searching for clutter the clutter count is incremented by eight in response to an input targert but is not decremented in the absence of a received target from that clutter mapping area. In any clutter mapping cell when the clutter count reaches a threshold within a selected number of scan periods, the reject code is set to the amplitude corresponding to the maximum amplitude target report received in that cell and provided by a temporary memory.

Abstract: An analog output circuit for a digital correlator that may be completely integrated with the digital correlator on a single CMOS/LSI chip. The output circuit includes a compensating arrangement so that its output voltage is substantially unaffected by internal processing variables between different chips or by external variables such as temperature or supply voltages. The circuit includes a reference MOS unit and a correlation MOS unit each including parallel arranged PMOS transistors respectively coupled in series with first and second NMOS transistors. An operational amplifier biased to a voltage V.sub.REF is coupled between the reference MOS unit and the gates of the first and second NMOS transistors.