Abstract: A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a shifted voltage threshold. Effectively, this voltage translator circuit has very little supply current (Icc) after the device switches. Specifically, the voltage translator in accordance with the present invention includes a first and second inverter coupled in series between an input node and an output node. A third inverter connects between the output node and a fourth inverter. A first circuit portion that establishes the low-to-high switching point connects between the fourth inverter and the first inverter. A second circuit portion connects between the fourth and first inverter that will block the switching current from draining the voltage supply after the transition from low-to-high has occurred.

Abstract: A distributed web CGI architecture is disclosed. According to one embodiment of the present invention, distributed web common gateway interface architecture includes a primary network having a primary server (304). A database (210) communicates with the primary server (304). A plurality of secondary networks (202) are provided, with at least one secondary server (302) in the secondary network (202). In another embodiment, a method for the distribution of data files in a distributed organization is provided. The distributed organization has a multiple networks that communicate with the primary server. The method involves the steps of (1) validating a data file at a secondary server in one of the networks; (2) correcting defects in the data file if the validation fails; (3) releasing a validated data file to the primary server; (4) and transferring the validated data file to the primary server.

Abstract: A “Design Zones” system provides a highly secure common resource computing environment or design zone with services on the common resource or design zone being protected by multiple layers of security to engagement boxes with the computing environment where the partners can work simultaneously in multiple teams, run simulation tests, emulate software problems and share in a secure zone with just the remote display going back to the engagement box and therefore to the partner outside the owner.

Abstract: For a given sentence grammar, speech recognizers are often required to decode M sets of HMMs each of which models a specific acoustic environment. In order to match input acoustic observations to each of the environments, typically recognition search methods require a network of M sub-networks. A new speech recognition search method is described here, which needs that is only the size of a single sub-network and yet gives the same recognition performance, thus reducing memory requirement for network storage by (M?1)/M.

Abstract: A highly secure “Design Zones” system is described that promotes collaboration between a manufacturer and owner of compute systems and its partners such as sub-contractors, customers and suppliers offers flexibility in the compute and design process. A partner starts a VPN tunnel between his workstations to establish a secure encrypted tunnel end to end wherein each partner is identified with a different VPN group/password. A session is started by the partner in a Web page on a portal machine through a thin client technology that authenticates thru LDAP the user/password of the person.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.

Abstract: The operating range of joint additive and convolutive compensating method is extended by enhanced channel estimation procedure that adds SNR-dependent inertia and SNR-dependent limit on the channel estimate.

Abstract: A system and method are implemented for preventing regulated supply undershoot in state retained latches of a leakage controlled system, using a voltage source depending on a reference voltage that includes a decay to resolve undesirable undershoot.

Abstract: An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20) is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit (10) are connected to serial input terminals (SERRX) of the integrated circuit (10). An attenuator (26), which in the disclosed embodiment includes programmable attenuators (30P, 30N) and a fixed attenuator (32), one of which is selected, is disposed in the loopback path. A deterministic jitter injector (28) is also in the loopback path, and may be implemented by way of variable length trace blocks (35P, 35N) on the test board (30).

Abstract: An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus for receiving an input signal from the receiving device and having at least one output locus for presenting an output signal for the receiving device; each respective at least one output locus presents an output signal in response to the input signal received at a respective input locus of the at least one input locus; (b) a feed forward circuit coupling each respective input locus with its respective corresponding output locus to provide a feed forward signal to the respective corresponding output locus; the feed forward signal is in phase with the input signal received at the respective input locus.

Abstract: An apparatus for use with a sensor includes first and second signal treating circuit segments coupled with the sensor for presenting a substantially balanced differential signaling representation of output signals from the sensor. Each respective signal treating circuit segment comprises a plurality of circuit elements having different electrical symmetries coupled in parallel and establishing a plurality of parallel signal paths having asymmetric signal handling characteristics. A feedback circuit is coupled with the first and second signal treating circuit segments and provides feedback signals to selected circuit elements in each of the first and second signal treating circuit segments. The feedback signals effect substantially balanced signal handling among the selected circuit elements having similar electrical symmetries.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract: A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface layer; a base contact (130 and 131) extending through a substantial portion (141) of the surface layer, spaced apart (140a) from the emitter; an insulator region (150/151) buried under the base contact; a collector contact (120); and a first polycrystalline semiconductor region (152/153) selectively located under the insulator region, and a second polycrystalline semiconductor region (154) selectively located under the collector contact. These polycrystalline regions exhibit heavy dopant concentrations of the first conductivity type; consequently, they lower the collector resistance.

Abstract: An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique “L” shaped pattern of geometric features, which is easily detected by the recognition system of e-beam imaging equipment, and is located in close proximity to the specific circuit features under investigation at each level to be inspected. The requirements for an alignment mark design which is recognizable by state-of-the-art e-beam imaging systems are enumerated, as well as the methodology for application. The alignment marks which are included at each critical step add no cost to wafer processing, and any design cost is easily overcome by reduction in process development time by using defect learning.

Abstract: A speech recognizer operating in both ambient noise (additive distortion) and microphone changes (convolutive distortion) is provided. For each utterance to be recognized the recognizer system adapts HMM mean vectors with noise estimates calculated from pre-utterance pause and a channel estimate calculated using an Estimation Maximization algorithm from previous utterances.

Abstract: For a given lookup table, maximum and minimum values of index values are determined. The lookup table is expanded in both directions by replicating the lowest and highest values to take care of these maximum and minimum values. This reduces the rendering clock count for each pixel.

Abstract: Servo error signal circuitry apparatus and methods are described. The difference between two bottom envelope signals SEbtm and SFbtm is calculated by a subtracter (40) to generate a difference signal (SEbtm?SFbtm). The difference signal (SEbtm?SFbtm) is input as an alignment signal (AL) to an equalizer (42) and as a basic tracking error signal to the positive input terminal of a second subtracter (52). On the other hand, the difference between two top envelope signals SEtop and SFtop is calculated by a third subtracter (48) to generate a difference signal (SEtop?SFtop). The signal K(SEtop?SFtop) obtained by multiplying a coefficient K with the difference signal using a coefficient multiplier (50) is input to the negative input terminal of the second subtracter (52). The difference signal {(SEbtm?SFbtm)?K(SEtop?SFtop)} output from the second subtracter (52) is used as an offset corrected tracking error signal.

Abstract: A biasing scheme is disclosed that helps reduce current noise in an associated device, such as, for example, a magneto-resistive device. The biasing scheme provides for setting a resistance path in a preamplifier, which is operative to energize the associated device, based on a biasing current that is to be used with associated device. Alternatively or additionally, the resistance path can be set based on a resistance of the associated device. As a result of setting the resistance path in this manner, noise through the associated device can be mitigated during its energization.

Abstract: The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the system comprises one or more hard disk drive integrated circuit chips residing on a board and a hard disk drive power plug receptacle residing on the board having two different value power supply ports associated therewith. The receptacle is operable to receive a power plug therein, wherein when the power plug is inserted therein in a proper orientation the two different value voltages are properly supplied to the one or more hard disk drive integrated circuit chips, and wherein when the power plug is inserted therein in an improper orientation the two different value voltages are switched with respect to their intended values. The system comprises a reverse power plug orientation protection circuit coupled between the hard disk drive power plug receptacle and at least one of the one or more hard disk drive integrated circuit chips.

Abstract: A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in the ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.