Abstract: A trace test and debug system for a target processor generates a program counter trace stream, a timing trace stream and a data trace stream. The target processor has three states, a program code execution state, an interrupt service routine code execution state, and a state where code execution is halted. The trace streams can be controlled so that the timing trace stream can be generated or excluded during the code execution halts. Similarly, when the timing trace stream is enabled for the interrupt service routine(s), the program counter and data trace streams can be selectively generated or excluded. The contents of the pipeline flattener can be held or flushed code execution halt depending on whether the pipeline is unprotected or protected. When the contents of the pipeline flattener are held during a code halt, the program counter trace stream and data trace stream is halted even if the timing trace stream remains active.

Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

Abstract: In an analog-to-digital converter used to convert and store in buffer registers signals from a plurality of peripheral devices, a mode is provided wherein, for selected peripherals, the most recent converted signal overlays the previously stored signal in the buffer registers.

Abstract: A method for performing time and frequency Signal-to-Noise Ratio (SNR) dependent weighting in speech recognition is described that includes for each period t estimating the SNR to get time and frequency SNR information ?t,f; calculating the time and frequency weighting to get ?tf; performing the back and forth weighted time varying DCT transformation matrix computation MGtM?1 to get Tt; providing the transformation matrix Tt and the original MFCC feature ot that contains the information about the SNR to a recognizer including the Viterbi decoding; and performing weighted Viterbi recognition bj(ot).