Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).
Abstract: A voltage level shifter circuit (10) for outputting an output high (18) and output low (18) signal is provided which accommodates multiple power supplies (12 and 22) at different relative voltage to each other. The voltage level shifter (10) includes an input stage (24) which is characterized by voltage ranges applicable to the process used to make the circuit. The voltage level shifter circuit includes an output stage (18) which is also characterized by the same voltage ranges which cannot be exceeded. The output stage outputs the translated output high (16) and output low (18) voltage signals. A clamping network (20) is employed to ensure that the output stage voltage ranges are not exceeded. The present invention implements a high voltage level shifter (10) using low voltage components by extending the breakdown capability of the voltage level shifter circuit (10) past the breakdown voltage of any single component in the circuit.
Abstract: A compact PLL circuit (100) and method of operation are provided which include a phase/frequency detector circuit (102), a control voltage generating circuit (110), and a VCO circuit (108) including at least one delay buffer circuit (118). A transmission gate (M3, M4) is arranged in series with each delay element (M5, M6) in the VCO circuit (108). A plurality of "power down" transistors (M3, M8-M9, M13-M16) are arranged strategically in the control circuit (110), and a "power down" transistor (M7) is arranged strategically in at least one delay buffer circuit (118). A filter arrangement (R1, R2, C) is included in the control circuit (110). Consequently, a relatively compact PLL circuit design is provided in which output jitter is minimized, the overall stability of the PLL is maximized, and only leakage current is drawn from the PLL circuit (100) during a "power down" mode of operation.
Abstract: A wide bandwidth, phase-stable amplifier circuit (10) and method is provided. Amplifier circuit (10) comprises amplifier cells (12a) and (12b) and a low impedance summing circuit (14). Each of amplifier cells (12a) and (12b) are biased at a predetermined bias current lower than a typical amplifier cell. The output of amplifier cells (12a) and (12b) are coupled to amplifier circuit (14) having transistors (30) and (32) coupled in a cascode configuration. By using the low bias current in amplifier cells (12a) and (12b) and the low impedance summing circuit (14), amplifier circuit (10) provides a wide bandwidth, phase-stable amplifier circuit.
Abstract: This invention relates to a process for strengthening the adhesive bond between a lead frame and a plastic mold compound (350). The process involves plating the lead frame with a copper strike and selectively exposing the copper strike to an oxidizing agent to form a layer of cupric oxide (CuO) (318). Such lead frames are fitted with chips (324) and then encapsulated in the plastic mold compound (350), whereby the adhesive bond forms directly between the layer of CuO (318) and the plastic mold compound (350). A lead frame produced by this process may include a plurality of leads (310) having lead ends (312) and lead fingers (314) and a die pad (320) having a layer of CuO (318). The die pad (320) is encased by a plastic mold compound (350) which forms an adhesive bond directly with the layer of CuO (318). This layer (318) may have a thickness in a range of about 5 to 50.mu. inches (12.7 to 127 .mu.cm). Lead ends (312 ) and lead fingers (314) may be spot-plated with silver or palladium.
Abstract: A method for electrically connecting integrated circuit copper-gold ball bond that connect a bond wire (18) with a bond pad (14) forms a palladium layer (16) in the electrical connection between the bond wire (18) and the bond pad (14). The connection avoids excessive stresses that arise from intermetallic formations between the bond wire (18) and the bond pad (14).
Abstract: A voltage reference circuit (2) is provided that operates with a minimal amount of headroom. A low threshold voltage transistor (M71) is incorporated into a bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) to eliminate base current errors that a current mirror (Q3 and Q4) of the bandgap may introduce. A low threshold voltage transistor (M72) is incorporated into the gain circuit (Q7) to eliminate base current error that a gain transistor (Q7) may introduce. A third low voltage transistor (M73) may be incorporated into a feedback circuit (QS) to eliminate any voltage variations possibly caused by the addition of the first two low threshold transistors (M71 and M72). Using P channel type MOS low voltage threshold transistors for base drive cancellation allows the circuit to operate effectively with a very low input voltage of around about 2.0 volts.
Abstract: A semiconductor package device is disclosed. In one embodiment, attached by its active face to a lead-on-chip leadframe having leadfingers is an integrated circuit. The integrated circuit has a polyimide coating on its backside. An encapsulating material surrounds the integrated circuit and the lead-on-chip leadframe so that the leadfingers are exposed. The polyimide coating on the backside of the integrated circuit helps to reduce package cracking arising from mounting the device to a printed circuit board by relflow solder.
February 16, 1994
Date of Patent:
July 18, 1995
Texas Instruments Incorporated
Thiam B. Lim, Tadashi Saitoh, Boon Q. Seow
Abstract: This invention relates to lead frames upon which chips (A or B) are mounted prior to encapsulation during IC device packaging. A lead frame structure (6) for manufacturing an IC device comprises a lead frame base (1) including a plurality of leads (10) and four first tie bar portions (16) extending toward a die pad aperture (17). A die pad (2) forms a cross-shaped mounting surface (20) for receiving a chip (30), wherein the mounting surface (20) is smaller than the chip (30), such that perimeter surfaces of the chip (30) are substantially exposed when the chip (30) is mounted on the mounting surface (20). Four second tie bar portions (21) extend from the mounting surface (20) and correspond to the four first tie bar portions (16). The die pad (2) is affixed to the lead frame base (1) and positioned in the aperture (17) by affixing each of the first tie bar portions (16) to a corresponding one of the second tie bar portions (21).
Abstract: A slope control circuit having a plurality of resistive elements connected in parallel, each of the resistive elements including a control element for causing the associated resistive elements to be one of electrically conductive or electrically nonconductive, a delay circuit having a plurality of delay components coupled together in series, each of the delay components having a predetermined delay, the junction of each different adjacent pair of the delay components being coupled to the control element of a different one of the resistive elements and a load circuit coupled across the plurality of resistive elements. The circuit can further include a delay adjust circuit for adjusting the delay of each of the delay components, either initially or on-line. The resistance of each of the resistive elements can be the same or different. The plurality of resistive elements and the delay components are all disposed on a single semiconductor chip.
Abstract: An adaptive transmission line termination which includes a variable voltage controlled resistor (16) connected either in series with the sending end of transmission line (10) or in parallel with the receiving end of line (10). The resistance of resistor (16) is varied in dependence upon the half voltage appearing on line (10) in order to match the characteristic impedance of line (10) for the series or source termination case. In the parallel termination case, the resistance of resistor (34) is varied in dependence upon the voltage appearing at the input of gate (14) to match the characteristic impedance of line (10).
Abstract: A lead over chip packaged device that is less prone to package cracking during surface mounting is disclosed. The lead over chip lead frame overlies the active face of a semiconductor circuit, The backside of the semiconductor circuit is covered with an ainopropyltriethoxysilane coating. The aminopropyltriethoxysilane coating promotes adhesion between the backside of the semiconductor circuit and the mold compound used to encapsulate the device. This reduces package cracking resulting from delamination between the inactive face of the chip and the mold compound during reflow solder.
Abstract: Spacing and stabilization guides for saw blades have a coating of a chemically vapor deposited silicon carbide on the face of the guide that contacts the saw blade. The guides may be fixed or rotatable on mounting brackets.
Abstract: A circuit (16) having an extended breakdown capability is provided for switching an inductive load driver (12). The circuit (16) includes a first switch (18) for providing a first drive voltage when the first switch (18) is closed. A second switch (20) is provided for receiving the first drive voltage from the first switch (18) and delivering the first drive voltage to the inductive load driver (12) when the second switch (20) is closed. The second switch (20) limits the voltage across the first switch (18) to a predetermined level when the first switch (18) is open. A third switch (22) provides a second drive voltage to the inductive load driver (12) when the third switch (22) is closed.
Abstract: An integrated power device comprises a power transistor (26) and a plurality of sense transistors (38), (40), (42), (44), and (46). Sense transistors (38), (40), (42), and (44) are constructed around the periphery of the active area occupied by power transistor (26). Sense transistor (46) is located within the interior of the active area occupied by power transistor (26) and contact is made to the necessary source region (64) of transistor (46) using a second level of metal interconnect to form a source contact (74).
January 4, 1993
Date of Patent:
April 18, 1995
Texas Instruments Incorporated
Joseph A. Devore, Ross E. Teggatz, Konrad Wagensohner
Abstract: An alignment process (30) for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.
Abstract: A programmable VCO circuit (300, 700) and method of use are provided whereby a current proportional to the strength of the NMOS process used to fabricate the circuit may be subtracted from the control current derived at the circuit's input, to compensate for process variations. Also, a programmable VCO circuit (300) and method of use are provided whereby a current developed from one-half the supply voltage for the VCO circuit may be subtracted from the control current derived at the circuit's input, in order to cause programmed gain changes to occur about the center of the control voltage range, and minimize output "jitter" when the VCO is used in a phase-locked loop. A gain compensation circuit (800) is also provided to linearize the gain of the programmable VCO circuit (300) for higher control voltage levels and thereby extend the VCO's effective operating range.
September 30, 1993
Date of Patent:
March 21, 1995
Texas Instruments Incorporated
Patrick P. Siniscalchi, William R. Krenik
Abstract: A method and apparatus for transmission line termination is provided in which a transmission line (12 and 14) is terminated by transmission gates (20 and 22) at a transmitter (24) and a receiver (26). The resistances of the transmission gates (20 and 22) are controlled by precision resistance control circuits (30 and 31), respectively. Precision resistance control circuit (30) uses a reference resistor (32) to control the resistance of the transmission gate (20).
Abstract: A method and system (10) are provided for monitoring an operating state of an engine (12). Data are measured (84) from the engine (12). The data are indicative of the operating state of the engine (12). The data are processed (86, 90, 92) according to a discrete Fourier transform. The operating state of the engine is monitored by processing (96-114) the discrete Fourier transform.
Abstract: A voltage reference circuit (2) is provided which includes a 2nd order curvature correction circuit (3) that eliminates undesirable 2nd order polynomial temperature dependency characteristics. A bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) forms a bandgap current (I.sub.X) that is dependent upon absolute temperature. A translinear cell (Q15, Q14, Q13, Q12, Q11 and Q10) transforms this current in a squaring transformation and divides the squared current by a temperature independent current (I.sub.X). A current mirror (Q17 and Q16) adjusts the value of the squared current so that it approximates the value of the 2nd order term of the bandgap reference circuit.