Abstract: The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a layer of gate oxide on the semiconductor wafer; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam is directed at the semiconductor wafer; an electron beam inspection tool used to detect passive voltage contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the energy levels vary from about 600 eV to 5000 eV.

Abstract: A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor wafer in proximity to the reticle; directing radiation through a first plurality of the pixels onto a first location on the wafer; changing the relative positions of the semiconductor wafer and the reticle; and directing radiation through a second plurality of the pixels onto a second location on the wafer. The first plurality of pixels can be used to form a first mark and the second plurality of pixels can be used to form a second mark, wherein the second mark is different from the first mark. The marks can be made of a pattern of dots in order to save space. The pixels can be selected to form certain marks by using a computer 304 to turn on or off a transistor that may be associated with each pixel. Also described is a system for marking a semiconductor wafer.

Abstract: A glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity inherent in the switching operation. During the switching from fast to slow clock domains the mechanism measures the uncertainty or ambiguity of the first slow clock cycle duration during the switching operation and stores this value. At some time later, during the slow to fast clock switching the clock switch mechanism compensates for the metastability of the first slow clock cycle during fast to slow switching using the ambiguity value previously measured. In this manner the fast and slow clocks are switched between each other in a glitch-free and self compensating manner.

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract: An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP2 is mirrored by the output current source IOUT that is desired to be increased. Without positive feedback, the gate of MN2 would be fixed by MP1 and MN1, and when input voltage VIN decreases by an incremental voltage &Dgr;V, the resulting current increase would distribute an increased voltage not only across MP2's VGS but also in the VGS of another transistor MN2; therefore, undesirably, not all of the &Dgr;V voltage change is mirrored in IOUT. However, if positive feedback such as MP5 is provided, the feedback dynamically increases the voltage at the gate of MN2. The increased voltage of MN2's gate essentially provides more voltage “headroom” for MP2 and MN2, and allows current through MP2 to increase with any voltage decrease in VIN.

Abstract: A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in the GFSK modulation scheme of “BLUETOOTH” or GSM, as well as the chip phase modulation of the 802.11b or Wideband-CDMA. The current gain of the DCO oscillator is predicted by observing past phase error responses to previous DCO corrections. DCO control is then augmented with the “open-loop” instantaneous frequency jump estimate of the new frequency control word.

Abstract: An improved bond integrity test system is provided by eliminating the spring loaded wire spool cover which contributes to particulate matter, and by addition of a second contact diverter in the wire path. These improvements have been shown to decrease false lifted ball bond reports by 68%, and therefore to improve productivity and accuracy of the test system. Such changes are readily adapted to current bonders, as well as to new designs.

Abstract: A voltage controlled oscillator (38) includes an LC tank (20) and a capacitor bank (21). LC tank (20) includes an inductor (12) and a varactor (14). The capacitive output of the varactor is controlled by a control voltage &ngr;. To electronically tune the voltage controlled oscillator, a set of capacitors (24) in the capacitor bank (21) are enabled by a digital control signal based on a frequency comparison with a desired frequency. Once the capacitor bank is set, the frequency can be locked at the desired frequency by the phase lock loop.

Abstract: The present invention provides, in one aspect, a method of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror array, on an assembly substrate. The method further includes coupling an assembly lid to the assembly substrate and over the MEMS device to create an interior of the MEMS assembly housing the MEMS device, whereby the coupling maintains an opening to the interior of the MEMS assembly. Furthermore, the method includes lubricating/passivating the MEMS device through the opening. In addition, a MEMS assembly constructed according to a process of the present invention is also disclosed.

Abstract: A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.

Abstract: A method for preconditioning a CMP polishing pad and retaining ring prior to semiconductor wafer polishing. In the method of the present invention, the retaining ring is lowered to contact the rotating polishing pad, and a cleaning chemistry of ammonium citrate is applied to the pad. In an alternative embodiment, the cleaning chemistry comprises an aqueous solution of ammonium citrate, and a surfactant and/or copper inhibitor. After a sustained preconditioning period in which the retaining ring and polishing pad are polished, the pad is rinsed, lowering particulate buildup on the pad between wafer polishing steps, and bringing defect levels into an equilibrium state prior to each wafer polishing step.

Abstract: A location determination apparatus, method and system (10, 23, 26, 32, 36, 48, 52, 60, 64, 74, 78, 84, 90, 106) that is an improvement upon existing location determining techniques. The invention enables precision indoor location determination through the use of non-DTV terrestrial broadcast signals (e.g. one way, wide area, dissemination of information)(20), or re-broadcast signals (44, 56, 70, 80) of the proposed (terrestrial based) digital satellite radio relay transmitters (42, 54) to provide position location. This solution does not require a local receiver to correct for long distance propagation dispersion, particularly for the satellite relay, as the digital radio satellites are already synchronized to GPS time.

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure.

Abstract: A circuit for detecting a transmit diversity signal comprises a first circuit (706) arranged to receive a first synchronization code. The first synchronization code is modulated by a data signal. The first circuit produces a first output signal. A second circuit (732) is arranged to receive a plurality of predetermined signals. The second circuit produces a channel estimate. A detection circuit (710, 712) is arranged to receive the first output signal and the channel estimate. The detection circuit produces a signal corresponding to the data signal.

Abstract: A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.

Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (240) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller (132) retrieves the header portion of the ATM packet from a transmit endpoint (240) and stores the information in registers (252, 254, 256) in the ATM transmit controller (132). A four-byte ATM cell header is then transmitted to byte buffers (268) and to the DSP (32) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint (240) in shared memory (44), and forwarded to byte buffers (268) for transmission.

Abstract: A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a function of the difference between the frequency (fref) of a reference signal and the output frequency (fvco) of the voltage controlled oscillator (12) and the oscillator contains as a frequency-influencing circuit element a varactor (14) whose capacitance value can be varied over a fine adjustment range by the control voltage for altering the output frequency. A variable capacitance (18) is provided which can be connected in parallel to the varactor (14) when there is a change in the frequency (fref) of the reference signal, the value of this capacitance (18) being adjustable as a function of the control voltage output by the phase/frequency detector (22).

Abstract: Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions for the thick gate oxide transistors are formed using a threshold voltage adjust implant, and lightly doped source/drain regions for the thin gate oxide transistors are formed using an LDD implant. The use of threshold voltage implantation to form the lightly doped source/drain regions for the thick gate oxide transistors allows lower dopant concentrations therein compared with the thin gate oxide transistors without the need for separate LDD implantation processing for transistors of different gate oxide thicknesses.

Abstract: Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the substrate to form an aperture (210) over a desired portion of the substrate near its outer edge. A buffer material (214), selected to impede mobile charge ingress, is implanted (310) through the aperture into the insulator layer (304) of the substrate to form a buffer structure (312).

Abstract: A frequency bin method of carrier frequency acquisition uses a plurality of predetermined carrier frequency offset bins. A single bin is selected from among the plurality of bins. A local VCO is then adjusted to remove the carrier frequency offset associated with the single selected bin. Carrier frequency acquisition is then attempted using the adjusted VCO. If successful, the receiver enters its steady state operating mode. If unsuccessful, a new bin is selected and the VCO is again adjusted using the new carrier frequency offset associated with the newly selected bin. The process is repeated until successful communication is achieved in association with a properly adjusted VCO.