Abstract: A system for transferring data between a pair of data processing units having system buses includes a plurality of memories in each of the data processing units; each memory having a random access portion and an associated sequential access portion; means for transferring data between each of the random access portions of each of the memories and its associated sequential access portion; and means connecting the sequential access portions of each of the memories in one of the data processing units to the sequential access portions of the other of said data processing units to permit data flow therebetween; the data flow between the sequential access portions of said memories occurring asynchronously of the remainder of the system so that the data processing units can utilize their system buses during such data flow.

Abstract: A method of operating a data processing system using virtual memory in which virtual memory addresses are formed by a base register value and a displacement value and are mapped to real memory addresses includes the steps of adding the base register value content and the displacement value, and simultaneously with the adding operation, performing a translation of the base register value to produce a virtual address corresponding to the base register value.

Abstract: A microcoded data processing system utilizes common microcode execution routines for both register-to-register operations and memory-to-register operations. The system includes a memory data register for storing an operand for use in a memory-to-register operation, a pair of address registers for containing the addresses of the registers to be involved in the execution of register-to-register instructions, and circuitry responsive to generation of an instruction indicating a memory-to-register operation for generating the address of the memory data register from one of the address registers, whereby the register-to-register operations and the memory-to-register operations can share common execution routines without any performance time penalty or any increase in required microcode.The system also provides for the simultaneous generation of the addresses of all registers to be employed in instructions involving multipart operands.

Abstract: A method of emulating the instructions of a target computer in the instructions of a host computer to operate the host computer in accordance with the target computer instructions, the target computer having the capability of modifying its own instructions and data during operation, includes the steps of storing the target instructions in a target memory segment, sequentially withdrawing the target instructions from the target memory segment and executing the target instructions in the host computer, constructing a template of the host instructions for each of the target instructions executed, storing each of the templates for reuse each time the corresponding target instruction is to be executed, limiting access to those target instructions in the target memory segment which have been stored in one of the templates to permit only read operations to be performed thereon, and detectng a target instruction which attempts a write operation on one of the target instructions which is in a stored template.

Abstract: A data processing system operates in a multiprogramming mode in which a plurality of different tasks are performed, at least one of the tasks being interruptable by another one of the tasks, and the system includes at least one facility which is not used by all of the tasks. The method of operating the system includes the steps of permitting access to the facility by a first task requesting such access, detecting the interruption by a second task of the first task prior to completion of the first task's use of the facility, and preventing access to the facility by any task until the data and state information in the facility relative to the first task has been stored outside the facility.

Abstract: Apparatus is provided for testing a data processing system which includes a microprocessor, the testing occurring with the microprocessor in place in the system. The apparatus comprises: a support microprocessor for controlling the testing, a serial-to-parallel and parallel-to-serial converter connected between the support microprocessor and the system microprocessor, means for supplying a series of level sensitive scan design (LSSD) test signals from the support microprocessor through the converter to the system microprocessor, and means for returning the results of the level sensitive scan design test signals from the system microprocessor through the converter to the support microprocessor.

Abstract: Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.

Abstract: Logic simulation is performed using special purpose hardware which operates in either one of two simulation modes. The machine allows detailed timing simulation where each device may be programmed with a delay time of zero, one, or multiple simulation time units. In addition, the machine supports zero and unit delay simulation in a high performance "unit delay" mode. The logic simulation function is partitioned into six sub-functions which are implemented in a single stage of a six-stage pipeline. The pipeline stages which implement the multi-unit delay time queue management may be switched to perform a different algorithm for unit delay simulation. The machine is able to perform extremely fast functional circuit testing and to perform detailed timing simulation without changing the circuit "netlist".

Abstract: A bus interface system for communicating between a master bus interface and a plurality of slave bus interfaces includes a plurality of lines extending between the master unit and each of the slave units, the lines including a clock line containing clock signals, a gated clock line containing gated clock signals having a frequency which is a submultiple of the frequency of the clock signals, a data line, a command register line, an active line, and circuitry for exchanging data between the master unit and one of the slave units on the data line under the control of the other lines.

Abstract: Apparatus is provided for improving the coupling between an external inductive transmitting coil and an internal inductive receiving coil to transmit power and/or data to the receiving coil from the transmitting coil. The structure includes a coupling coil inductively coupled to the transmitting coil to increase the Q factor and hence the energy transfer between the transmitting coil and the receiving coil.

Abstract: A simulation technique for modeling the function of logic elements containing memory is disclosed. The technique uses a table to represent the logical function of the devices that are being simulated.

Abstract: A control system is provided for a processing container line to detect the occurence of a jam or other malfunction within the line. The system compensates for the initialization of the line when a number of containers enter the line before any are discharged therefrom. The system also allows for a tolerable limit on the number of containers which may become "lost" in the processing line without indicating a jam in the line.

Abstract: An adjustable arm for controlling the horizontal and vertical position of an object mounted at one end of the arm comprises:means for rigidly mounting the end of the arm opposite the end at which the object is mounted;a plurality of interconnected links, a first group of the plurality of links controlling the horizontal position of the arm and the object; anda counterbalancing link among the plurality of links, the counterbalancing link being disposed intermediate the first group of links, the counterbalancing link serving to provide vertical movement of the plurality of links and the object and to counterbalance the weight of the object at the one end of the arm.

Abstract: Apparatus for determining the dielectric constant of a fluid as a measure of possible contaminants therein. A reference fluid sample having a known dielectric constant is first placed in a capacitive dielectric sensor and then the fluid to be analyzed is placed in the sensor. By comparing the measured values, an indication is provided of the degree of contamination of the analyzed fluid.

Abstract: For characterizing coating compositions with magnetic particles the coating composition is subjected to an alternating magnetic field of variable frequency. The field induced by the coating composition after energization is recorded, and thus the susceptibility of the coating composition is measured. Depending on the variable frequency, conclusions can be made regarding the degree of dispersion, particle density, and viscosity of the coating composition. The variable frequency is between 1 and 100 cps, and the field intensity of the energizing field should be lower than 10 Oerstedt. The coating composition is fluid or stagnant in a pipe *1, 11 which is surrounded by field coil and measuring coil.

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. The resistance of each corresponding link in each of the four quandrants in the array is compared with the resistance of an array of reference fusible links to detect the presence or absence of a short circuit.

Abstract: A head positioning system with automatic gain control for use in disk information storage apparatus employs multiphase radial position error signals derived from position reference information on the disk to control the position of a transducing head by means of a head positioning actuator. A variable gain amplifier amplifies the signals from the transducing head prior to their application to a position error signal generating means. The gain of the amplifier is controlled in a gain control loop by a gain function. The gain function is derived by combining the differnet phase position error signals to provide, at any position of the head, a measurement of the rate of change of the position error signals per track of displacement. This system affords gain control which is substantially independent of head width and limits variations in offtrack gain between heads.

Abstract: A servo system for a magnetic disk file having a voice coil motor (VCM) actuator generates a position error signal (PES) from servo information recorded on one of the disks. An electrical model of the VCM is employed through which a measure of the VCM electrical current is passed to generate a simulated PES signal which is continuous even if the regular PES is sampled or intermittent.

Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the CONTROL function comprises one or more of the remainder of the set of input variables.