Abstract: A satellite communication system for delivering simplex messages to subscribers comprises multiple Message Origination Controllers (MOCs), one or more Message Termination Controllers (MTCs), satellites, and geographically-diverse communication units. Messages destined for particular communication units are transmitted to the one or more MTCs. The one or more MTCs then schedule delivery of the messages to communication units by employing a blocked timing structure for delivery of the messages. The one or more MTCs transmit the scheduled messages to satellites which broadcast the messages to communication units at the scheduled time. Communication units are assigned specific timing blocks during which they monitor radio signals for messages directed to them. During non-assigned timing blocks, communication units remain in a low-power state.

Abstract: Method and apparatus for packaging electronic equipment comprise a housing and a "midplane" that is removably secured to suitable flanges centrally located within the housing. Individual sub-modules (CPU, disk drive, I/O unit, power supply, etc.) have suitable electrical connectors which mate with corresponding connectors on the midplane. The sub-modules are inserted into the midplane from different sides of the housing. The exposed, outer surfaces of the sub-modules may either be finished in final form, or suitable bezels may be placed over the sides of the housing so that the sub-modules can be appropriately accessed for necessary replacement or repair.

Abstract: A programmable data envelope detector indicates the presence of phase encoded data being transmitted to or received from a data storage medium. The detector generates an output signal at a predetermined time after detecting the presence of data and continues to provide such output signal for a predetermined time after detecting the end of data. The detector comprises a data pulse detector, three-count up-down counter, two multicount four-bit up-down counters, a microprogrammable control store and decoder, a compare circuit, and a latch circuit. The time periods at which the latch circuit generates the output signal are different depending upon the nature of the data transfer operation, such time periods corresponding to different microinstructions in the control store.