Abstract: An intramedullary screw and fixation system for intraosseous bone fusion of the subtalar joint includes a lag screw member, a reamer for reaming an internal surface of each of the calcaneus and talus medullary canals, and targeting guide assembly for alignment with the subtalar joint. The lag screw member includes an elongated body, a first threaded portion at a first end and a bulbous portion at a second end. The targeting guide assembly receives a cutting blade in an elongated rod for reaming the articulating surfaces of the calcaneus and talus intramedullary canals, where the cutting blade is inserted through a percutaneous incision into the elongated rod.

Abstract: An intramedullary fixation assembly for bone fusion includes a first member positioned at a proximal end of the intramedullary fixation assembly, and a second member positioned at a distal end of the intramedullary fixation assembly. The first member is slideably coupled to the second member and provides for an interference fit with the second member. The intramedullary fixation assembly includes an optional cannulated threaded screw member having a plurality of threads on an external surface of the threaded screw member.

Abstract: An intramedullary fixation assembly for bone fusion includes a first member positioned at a proximal end of the intramedullary fixation assembly, where the first member includes a plurality of first and second retaining screws, and a second member positioned at a distal end of the intramedullary fixation assembly, where the second member includes a plurality of third and fourth retaining screws. The first member is slideably coupled to the second member and provides for an interference fit with the second member.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: A fixation system, including an intramedullary fixation assembly and an instrument for coupling the intramedullary fixation assembly to bones. The intramedullary fixation assembly includes a proximal screw member positioned at a proximal end of the intramedullary fixation assembly, a distal member positioned at a distal end of the intramedullary fixation assembly, where the proximal screw member is slideably coupled to the distal member and makes a fixed angle with the distal member.

Abstract: The fragrance emanation system includes a container for holding preferably a fragranced liquid or gel, a housing for holding the container, and a wick. The housing contains a socket for attaching to the container, a cavity for receiving the container and a door for enclosing the container. One end of the wick protrudes from the container. An electrical circuit is included having a heater for heating the protruding end of the wick and electrical connectors coupled to the circuit to receive current from a power source to provide the current to the heater. The heater heats and evaporates the liquid within the wick, thereby accelerating the emission of vapors from the evaporated liquid. The door includes a window, a bottom and a mechanism for holding the door closed to assist in holding the container in engagement with the socket.

Abstract: In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes MxN capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: A semiconductor system in a package in which at least first and second semiconductor substrates are mounted one above the other on a package substrate. The first substrate is mounted on the package substrate with its active (or front) side facing the package substrate. A plurality of through-silicon-vias (TSVs) extend through one or more peripheral regions of the first substrate; and a redistribution layer is located on the back side of the first substrate and connected to the TSVs. The second substrate is mounted on the first substrate and electrically connected to circuits in the active side of the first substrate through the redistribution layer and the TSVs. Illustratively, one of the substrates is an FPGA and one or more of the other substrates stores the configuration memory and/or other functional memory for the FPGA. Advantageously, design costs are reduced by using pre-existing designs and modifying them as needed to provide TSVs along the periphery of the circuit.

Abstract: The disclosed methods and apparatus relate generally to the electronics media industry, such as cable television (CATV), home shopping services, on-line computer services and computer memory applications. These methods and apparatus allow a user to access and make use of electronic media input and output devices by reference to and/or utilization of standard printed matter, such as magazines, textbooks, or any other printed matter that can be correlated to electronic media.

Abstract: The disclosed methods and apparatus relate generally to the electronics media industry, such as cable television (CATV), home shopping services, on-line computer services and computer memory applications. These methods and apparatus allow a user to access and make use of electronic media input and output devices by reference to and/or utilization of standard printed matter, such as magazines, textbooks, or any other printed matter that can be correlated to electronic media.

Abstract: A method and system that limits the use of a communication device present in an area controlled by an intelligent controller. The intelligent controller detects any present communication devices in the area and conducts an inventory providing information about each detected device. The intelligent controller compares that information to a standard of use data, which specifies the conditions need to be present for allowing the usage of a communication device. If such conditions are not met, the intelligent controller sends commands to the communication device to restrict its functionality. Else if, the intelligent controller is incapable of restricting the communication device, it can notify authorities of unauthorized usage of a communication device in the restricted area.

Abstract: To improve noise rejection, a native (or undoped) NMOS transistor is used as a source follower in place of a conventional common source PMOS transistor in a voltage regulator circuit. The native transistor has a threshold voltage of approximately 0 volts which allows the maximum voltage output of the regulator to be higher by one threshold voltage of a conventional NMOS transistor than might be obtained from a voltage regulator that used a conventional NMOS transistor. Alternatively, a depletion transistor can be used to provide even higher output. In another illustrative embodiment, a conventional bandgap reference circuit is modified by replacing a common source transistor connected to the output of an op amp with a native MOS transistor connected as a source follower.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: In one embodiment, differential signaling and ground contacts are located in a rectilinear array of rows and columns with ground contacts spaced apart by three times the pitch distance between adjacent rows or columns and signaling contacts are located immediately adjacent the ground contacts. In particular, the two contacts of each differential pair are located one pitch distance apart from each other and one contact of each differential pair of contacts is located one pitch distance from a ground contact and the other contact of the differential pair is located approximately sqrt(2)*pitch distance from the same ground contact. In a second embodiment, differential signaling and ground contacts are located in a hexagonal array with ground contacts located three times the pitch distance between adjacent contacts and signaling contacts located immediately adjacent the ground contacts.

Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

Abstract: The present invention relates generally to mass spectrometry and the analysis of chemical samples, and more particularly to ion guides for use therein. The invention described herein comprises an improved method and apparatus for transporting ions from a first pressure region in a mass spectrometer to a second pressure region therein. More specifically, the present invention provides a segmented ion funnel for more efficient use in mass spectrometry (particularly with ionization sources) to transport ions from the first pressure region to the second pressure region.