Patents Represented by Attorney Watchstone P+D, plc
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Patent number: 7502348Abstract: In some embodiments, a silent proactive handoff is performed wherein a mobile device that is using a current network to transport its application traffic uses its silent periods to connect to at least one target network temporarily and uses this temporary connectivity to perform actions needed for handoff into the target network. Among other things, with such a silent proactive handoff approach, e.g., if handoff actions to a target network fail during silent periods, there can still be essentially no impact on the applications.Type: GrantFiled: April 1, 2005Date of Patent: March 10, 2009Assignees: Toshiba America Research, Inc., Telcordia Technologies, Inc.Inventors: Tao Zhang, Raziq Yaqub
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Patent number: 7332939Abstract: A comparator system for comparing a level of an input signal with a level of a reference signal comprises a first comparator configured to input the input signal to one of input terminals thereof and the reference signal to the other of input terminals thereof, a second comparator configured to input the reference signal to one of input terminals thereof and the input signal to the other of input terminals thereof, and a control circuit configured to input an output of the first comparator and an output of the second comparator. The control circuit selects one of the outputs of the first and second comparators quicker in level change timing, and controls an output signal of the control circuit at the level change timing of the selected output.Type: GrantFiled: September 13, 2004Date of Patent: February 19, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Shinichi Yamasaki, Masanori Okubayashi
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Patent number: 7271636Abstract: In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.Type: GrantFiled: October 28, 2005Date of Patent: September 18, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroya Yamamoto, Masahiro Umewaka, Shinji Osugi
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Patent number: 7253027Abstract: A method of manufacturing a hybrid integrated circuit device includes the steps of forming a plurality of units each including a conductive pattern on a surface of a board made of metal, forming grooves along boundaries of the respective units of the board, electrically connecting circuit elements to the conductive patterns in the respective units, separating the respective circuit boards by dividing the board along the grooves, and flattening side surfaces of the circuit boards by pressing the side surfaces.Type: GrantFiled: December 22, 2004Date of Patent: August 7, 2007Assignee: Sanyo Electric Co., Ltd.Inventor: Masaru Kanakubo
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Patent number: 7250352Abstract: In preferred embodiments, a method of manufacturing a hybrid integrated circuit device is provided, in which a plurality of circuit substrates 10 are manufactured from a single metal substrate 10A? by dicing. In some embodiments, the method includes: preparing a metal substrate 10A? having an insulating layer 11 formed on the top surface thereof; forming a plurality of conductive patterns 12 on the top surface of insulating layer 11; forming grooves 20 in lattice form on the rear surface of metal substrate 10B?; mounting hybrid integrated circuits onto conductive patterns 12; and separating individual circuit substrates 10 with, for example, a rotatable cutter.Type: GrantFiled: April 24, 2003Date of Patent: July 31, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Masahiko Mizutani, Sadamichi Takakusaki, Motoichi Nezu, Kazutoshi Motegi, Mitsuru Noguchi
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Patent number: 7232957Abstract: An object of the present invention is to provide a method of manufacturing a hybrid integrated circuit device, in which multiple circuit boards are manufactured from one large metal board by dicing. The hybrid integrated circuit device of the present invention includes a circuit board with a surface provided with an insulating layer, and conductive patterns provided on the insulating layer. Circuit elements are electrically connected to the conductive patterns. Further, each side surface of the circuit board includes a first inclined portion extending obliquely downward from a peripheral portion of the surface of the circuit board, and a second inclined portion extending obliquely upward from a back surface of the circuit board and formed to be larger than the first inclined portion.Type: GrantFiled: September 15, 2004Date of Patent: June 19, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Masahiko Mizutani, Mitsuru Noguchi, Nobuhisa Takakusaki
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Patent number: 7231307Abstract: In some embodiments, a temperature measuring apparatus is provided with a light receiving portion having a plurality of light receiving units for measuring heat quantity of divided temperature detecting area in a noncontact manner, a thermal sensor for detecting temperature of each of the plurality of light receiving units, a calculation portion for calculating a temperature of each of the divided temperature detecting areas based on the temperature obtained by the thermal sensor and the relative temperature difference obtained by the light receiving portion, a correction information holding portion for holding correction information on known reference temperature of the temperature detecting area and its corresponding calculated result outputted from the calculation portion obtained when heat quantity of the temperature detecting area is set to the reference temperature, and a correction portion for correcting the calculated result of the calculation portion based on the correction information.Type: GrantFiled: August 11, 2005Date of Patent: June 12, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Youji Takei, Masao Tsukizawa
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Patent number: 7218549Abstract: A memory cell and method of destabilizing a memory cell for facilitating a write operation are provided. A stability switch is coupled between one of a voltage supply or a ground terminal and the memory cell, and is turned off during the write operation to reduce the drive voltage required to drive a bit value into the memory cell.Type: GrantFiled: January 31, 2005Date of Patent: May 15, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Atsushi Kawasumi
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Patent number: 7213120Abstract: A circuit for prevention of unintentional writing to a memory prevents unintentional writing to a nonvolatile memory, after a recovery from a transitory power failure. The circuit includes a low-voltage detection circuit for detecting a power supply voltage drop depending on the state of a control signal for the detection circuit. A writing operation to the memory is prohibited depending on the control signal as well as upon an output signal of the low-voltage detection circuit.Type: GrantFiled: March 26, 2004Date of Patent: May 1, 2007Assignee: Sanyo Electric Co., Ltd.Inventor: Kazuo Hotaka
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Patent number: 7206218Abstract: A memory cell, including a word line, a bit line, a first node storing a bit value voltage level, a driver transistor coupled between the first node and a ground level, and at least one data transfer transistor having a gate electrode coupled to the word line, a source electrode coupled to the bit line, and a drain electrode coupled to the first node, wherein a channel length of the at least one data transfer transistor is smaller than a channel length of the driver transistor. By making the channel length of a data transfer transistor smaller than that of a driver transistor to which the data transfer transistor is coupled, operation speed and in particular read operation speed of the memory cell is improved, while maintaining memory cell stability.Type: GrantFiled: January 31, 2005Date of Patent: April 17, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Atsushi Kawasumi
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Patent number: 7202787Abstract: A non-authentic article discrimination system for discriminating whether an article to which an IC tag is attached is a non-authentic article includes an IC tag and a base device. The IC tag includes a first antenna portion for receiving a radio wave, a power generation circuit for generating electric power from the radio wave received by the first antenna portion, a first storing portion for storing information regarding the article, and a radio wave output circuit for outputting a radio wave including the information stored in the first storing portion via the first antenna portion.Type: GrantFiled: September 29, 2004Date of Patent: April 10, 2007Assignee: Sanyo Electric Co., Ltd.Inventor: Tsutomu Nakazawa
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Patent number: 7173457Abstract: A silicon-on-insulator (SOI) sense amplifier for sensing bit values stored in a memory cell, includes first and second input field effect transistors (FETs), connected to first and second cross-coupled CMOS inverter FET pairs. The input FETs are implemented as floating body FETs, which decreases gate capacitances and increases sense operation speed. History effect problems are minimized as threshold voltage differences are kept small.Type: GrantFiled: January 31, 2005Date of Patent: February 6, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Atsushi Kawasumi
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Patent number: 7152316Abstract: To provide a hybrid integrated circuit device in which the rear surface of a circuit board is exposed to the outside and a method of manufacturing the same. Here, leads are fixed to the surface of the circuit board along one side thereof. A method of manufacturing a hybrid integrated circuit device includes the steps of forming an electric circuit which includes a conductive pattern formed on a surface of a circuit board and a circuit element electrically connected to the conductive pattern, fixing a lead to a pad formed of the conductive pattern, housing the circuit board in a cavity of molds, and fixedly supporting the lead by clamping the lead between the molds, and performing sealing by filling inside of the cavity with sealing resin with the rear surface of the circuit board made in contact with an inside bottom surface of the molds.Type: GrantFiled: December 22, 2004Date of Patent: December 26, 2006Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Haruhiko Mori, Masaru Kanakubo, Hideyuki Sakamoto