Abstract: An unreliable training set is modified to provide for a reliable training set to be used in supervised classification. The training set is modified by determining which data of the set are incorrect and reconstructing those incorrect data. The reconstruction includes modifying the labels associated with the data to provide for correct labels. The modification can be performed iteratively.

Abstract: The present invention describes a system and process for measuring the performance of programs by means of messages, in particular with distributed programs. A corresponding area for performance and/or time entries is added to the message which is to be processed. At each processing stage of the message, a performance and/or time marker is deposited in this area. The performance and/or time marker consists essentially of the identifier of the computer, the identifier of the particular processing stage, a description of the particular processing stage, and performance data and/or a value of the computer time. All the performance and time markers are written into a file for later evaluation, so that data is available at the same time. Thanks to the integrated processing of performance data with application data, the performance analysis, e.g. of response times of definable processing procedures, in particular with distributed networks, is considerably simplified.

Abstract: A new noise control circuit which connects the sense ground node to ground in two specific period of times so that the NSA bouncing is minimized. Preferably these two periods are at the beginning of setting the n-type latch and when the data is transferring and CSL is switching. A pulse of NSET and together with whole CSLEN signal are used to activate the noise control circuit. The noise control circuit can also include a n-FET diode with its gate connected to the source and its drain tied to the Vbleq power supply. It is more preferable to use a low threshold voltage of n-FET device with Vt at 0.55 volts to form the clamp diode.

Abstract: The present invention provides a memory system that optimizes, during a sleep mode, a refresh period for a memory device, such as DRAM, which stores meaningful data and for which a refresh operation is required to prevent the loss of data.

Abstract: Methods for the ready identification of dynamic defects using switching induced light emission from CMOS gates in complex integrated circuits such as microprocessors are described. The rapid increase in the complexity of logic circuits means that practical gate level identification of the sources of dynamic errors will require methods other than the gate by gate tracing of every possible path taken by a given set of instructions. The methods described here are based on the ability of picosecond imaging circuit analysis to detect the switching activity of every gate of a complex circuit in a single, passive measurement, and the ability of data processing today to compare large two- and three-dimensional files.