Abstract: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Abstract: Methods and apparatus for merging two or more networks are disclosed. In one embodiment, a first switch of a first network receives a second set of information including routing identifiers associated with a second network, wherein the first switch of the first network is connected to a second switch of the second network. The first switch of the first network transmits a first set of information including routing identifiers associated with the first network. The first switch determines whether a conflict exists between the second set of information and the first set of information. A conflicting one of the routing identifiers associated with the first or second network may be transitioned to a non-conflicting routing identifier according to the determination of whether a conflict exists between the first set of information and the second set of information, thereby enabling data to flow between the first network and the second network via a link between the first switch and the second switch.

Abstract: An overlay mark for determining the relative shift between two or more successive layers of a substrate and methods for using such overlay mark are disclosed. In one embodiment, the overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern.

Abstract: According to the present invention, methods and apparatus are provided to improve the link state routing protocol (LSRP) to prevent transient loops during topology changes. Broadcast and shared multicast traffic may be dropped on particular ports upon detecting link state change until neighboring nodes have computed routes using updated link state information. An acknowledgment is sent upon receiving a link state record. Sync and sync-ack packets are used to determine when link state information is synchronized with that of peer nodes.

Abstract: A title management apparatus resident on a first computer including a memory for storing a control program and data, and a processor for executing the control program and for managing the data. The apparatus includes a title object resident in the memory including a title structure, the title structure further comprising a content element, a set of attributes, and a set of title object security indicia. The apparatus further includes an authorization structure configured to selectively redeem the content element based at least in part on the user security indicia, and further configured to use a set of protocols. The apparatus also includes a title management structure configured to associate a user with the title object based at least in part on the user data and the title attributes.

Abstract: A heterogeneous device including multiple types of resources is provided to implement multiple logic functions. Logic functions are provided with multiple configuration options. In one example, an optimal set of configuration options along with a target device are selected using cost and resource availability information associated with multiple heterogeneous programmable chips and the configuration options provided with the logic blocks.

Abstract: A duplexed network system is formed with a plurality of programmable controllers and two different networks. Each of the programmable controllers includes a CPU unit, a primary communication unit connected to one of these networks (the first network) and a secondary communication unit connected to the other of the networks (the second network). The primary communication unit serves to compile participation status of nodes connected to the first network. The CPU unit gives priority to the primary communication unit when a request to transmit a communication command is issued to both the primary and secondary communication units.

Abstract: Embodiments of the invention support improvements in network performance in networks such as storage area networks. This is particularly important in networks such as those implementing virtualization. These improvements, therefore, support improved mechanisms for performing processing in network devices such as switches, routers, or hosts. These improvements include various different mechanisms which may be used separately or in combination with one another. These mechanisms include methods and apparatus for processing traffic in an arbitrated loop, performing striping to support fairness and/or loop tenancy, performing configuration of network devices such as switches to enable virtualization to be performed closest to the storage device (e.g., disk), ascertaining a CPU efficiency that quantifies the impact of virtualization on a processor, and configuring or accessing a striped volume to account for metadata stored in each storage partition.

Abstract: Switches for a variety of circuits for different purposes are formed by using a plurality of similarly designed contact modules each having a module case incorporating a normally closed or normally open contact mechanism and a plunger for operating this contact mechanism, a single actuator having two end parts and being biased so as to rotate around a supporting axis between these contact modules, this actuator undergoing a rotary motion if a force is applied to one of its end parts so as to operate the plunger of an associated one of the contact modules with at least one of the end parts, a switch case that contains the contact modules and the actuator, and a push button for applying a force on one of the end parts of the actuator from outside the switch case.

Abstract: This invention provides for novel human antibodies that specifically bind to c-erbB-2. The antibodies may be used alone or as components of chimeric molecules that specifically target and deliver effector molecules to cells overexpressing c-erbB-2.