Abstract: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form titanium silicide on a surface of a silicon-containing substrate.

Abstract: An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The second source/drain may be included in a digit line inner conductor connecting a digit line to a transistor channel of the vertical transistor. The channel may include a semiconductive upward extension of the combined first electrode and first source/drain. The memory cell may be included in an array of a plurality of such memory cells wherein the second electrode is a common electrode among the plurality. The memory cell may provide a straight-line conductive path between the first electrode and a digit line, the path extending through the vertical transistor.

Abstract: The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.

Abstract: The invention encompasses a radiation-patterning tool. The tool is configured to be utilized to print a pair of structures in a radiation-sensitive material. The tool includes two separate and discrete features, with one of the features corresponding to one of the structures of the pair of structures and the other of the two features correspond to the other of the structures. At least one element is between the features. The at least one element is at least partially transparent to radiation passing through the radiation-patterning tool, but does not correspond to a discrete structure printed in the radiation-sensitive material. The element modifies the structures printed from the pair of features. The invention also includes printing methods and methods of forming aligned structures with radiation-sensitive material.

Abstract: An RF tag system, comprising an RF reader configured to issue a plurality of different RF commands and to provide a continuous RF illumination field, and a plurality of RF tags respectively including a permanent identification; wherein the plurality of RF tags are configured to respond to a certain RF command from the RF reader by transmitting their respective identifications by way of backscatter modulation of the RF illumination field, and wherein the RF tags are further configured to perform the responding by way of respective independently selected random radio frequencies and timeslots from respective pre-defined ranges of radio frequencies and timeslots.

Abstract: The invention includes a physical vapor deposition target composed of a face centered cubic unit cell metal or alloy and having a uniform grain size less than 30 microns, preferably less than 1 micron; and a uniform axial or planar <220> texture. Also described is a method for making sputtering targets. The method can comprise billet preparation; equal channel angular extrusion with a prescribed route and number of passes; and cross-rolling or forging subsequent to the equal channel angular extrusion.

Abstract: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has an electrically conductive interconnect extending therethrough. The interconnect electrically connects with the semiconductive material projection, and comprises a different dopant type than the semiconductor material projection. The invention also includes a method of bonding a first monocrystalline semiconductor substrate construction to a second monocrystalline semiconductor substrate construction, wherein the first construction is doped to a first dopant type, and the second construction is doped to a second dopant type different from the first dopant type.

Abstract: The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: In a system for flushing at least one internal space of an objective, in particular an exposure projection objective for semiconductor lithography, flushing is performed by mixing at least two inert gasses in such a way that the refractive index resulting therefrom corresponds at least approximately to the refractive index of air.

Abstract: The invention includes integrated circuitry having an electrically insulative layer over a substrate and an opening within the electrically insulative layer. The opening has a periphery defined at least in part by a bottom surface and a sidewall surface. A first titanium layer is disposed within the opening in contact with the bottom surface and is thicker along the bottom surface than along the sidewall. A layer of TiN is provided over the first titanium layer along the bottom surface and along the sidewall surface of the opening, and a second layer of titanium is disposed over the electrically insulative layer but substantially not within the opening. The second titanium layer has a thickness of less then 50 Å along the sidewall surface and over the bottom surface. An aluminum-comprising layer is within the opening and over the second layer.

Abstract: In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a volatile form; and d) volatilizing the volatile form of the component from the mass to leave a void region associated with the substrate.

Abstract: The invention encompasses polishing systems for polishing semiconductive material substrates, and encompasses methods of cleaning polishing slurry from semiconductive substrate surfaces. In one aspect, the invention includes a method of cleaning a polishing slurry from a substrate surface comprising: a) providing a substrate surface having a polishing slurry in contact therewith; b) providing a liquid; c) injecting a gas into the liquid to increase a total dissolved gas concentration in the liquid; and d) after the injecting, providing the liquid against the substrate surface to displace the polishing slurry from the substrate surface.

Abstract: Disclosed is an impact shoe system generally for use in rock crushers, namely centrifugal rock crushers. This impact shoe system generally includes a plurality of wear inserts patterned within the impact shoe to substantially reduce the wear on the impact shoe, as well as to increase the useful life of the impact shoe.

Abstract: Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of conductive lines which extend within a memory array area and a peripheral area outward of the memory array. Capacitor container openings and contact openings are contemporaneously etched over the memory array and conductive line portions within the peripheral area respectively. In another embodiment, a patterned masking layer is formed over a substrate having a plurality of openings formed within an insulative layer, wherein some of the openings comprise capacitor container openings within a memory array and other of the openings comprise conductive line contact openings disposed over conductive lines within a peripheral area outward of the memory array.

Abstract: A capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface.

Abstract: In one aspect, the invention encompasses a semiconductor circuit construction including a material which comprises Q, R, S and B. In such construction, Q comprises one or more refractory metals, R is selected from the group consisting of one or more of tungsten, aluminum and silicon, S is selected from the group consisting of one or more of nitrogen and oxygen, and B is boron. Also, in such construction R and Q do not comprise a common element. In another aspect, the invention encompasses a method of forming a capacitor. A first capacitor electrode is formed, a diffusion barrier layer is formed proximate the first capacitor electrode, and a dielectric layer is formed to be separated from: the: first capacitor electrode by the diffusion barrier layer. A second capacitor electrode is formed to be separated from the first electrode by the dielectric layer.

Abstract: In one aspect, the invention encompasses a method for electronic tracking of units originating from a common source which comprises a plurality of units physically joined with one another. A first transponder is physically associated with the common source, and the source is split to separate it into three or more of the units. A second transponder is physically associated with one of the three or more units, and the second transponder sends a code. The code of the second transponder is electrically associated with an identifier of the common source. In a particular aspect, the common source is an animal carcass.