Abstract: In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer. In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate. In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.

Abstract: A chemical vapor deposition method of forming a high k dielectric layer includes positioning a substrate within a chemical vapor deposition reactor. At least one metal comprising precursor and N2O are provided within the reactor under conditions effective to deposit a high k dielectric layer on the substrate comprising oxygen and the metal of the at least one metal precursor. The N2O is present within the reactor during at least a portion of the deposit at greater than or equal to at least 90% concentration by volume as compared with any O2, O3, NO, and NOX injected to within the reactor. In one implementation, the conditions are void of injection of any of O2, O3, NO, and NOX to within the reactor during the portion of the deposit. In one implementation, a capacitor is formed using the above methods. In preferred implementations, the technique can be used to yield smooth, continuous dielectric layers in the absence of haze or isolated island-like nuclei.

Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.

Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

Abstract: In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated.

Abstract: The present invention provides wireless communication and identification packages, communication systems, methods of identifying an identification device, methods of communicating, and methods of forming a communication device. In one aspect of the present invention, a wireless communication package includes a communication device having a substrate; communication circuitry borne by the substrate, the communication circuitry being configured to at least one of process and form wireless communication signals; and at least one antenna electrically coupled with the communication circuitry, the antenna being configured to at least one of receive wireless communication signals and output wireless communication signals; and an appendage coupled with the communication device, the appendage being configured to enhance at least one of receiving and outputting of wireless communication signals via the antenna.

Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.

Abstract: The invention includes a semiconductor processing method which comprises forming a first material layer over a substrate. A second material layer is formed over the first material layer. Photoresist is deposited over the second material layer, and an opening is formed within the photoresist to the second material layer. The second material layer is etched through the photoresist opening to a degree insufficient to outwardly expose the first material layer. The photoresist is then stripped from the substrate. Subsequently, the second material layer and the first material layer are blanket etched.

Abstract: In accordance with one aspect of the invention, a semiconductor processing method of treating a semiconductor wafer provides a wafer within a volume of liquid. The wafer has some electrically conductive material formed thereover. The volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere and at a temperature of at least 200° C., and below and within 10% of the melting point of the electrically conductive material. In accordance with another aspect, the volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere. After establishing the pressure of greater than 1 atmosphere, the pressure of the volume of liquid is lowered to a point effective to vaporize said liquid and the vapor is withdrawn from the chamber.

Abstract: In one aspect, the invention encompasses a transistor device comprising a region of a semiconductor material wafer, and a transistor gate over a portion of the region. The transistor gate has a pair of opposing sidewalls which are a first sidewall and a second sidewall. The device further comprises a pair of opposing sidewall spacers adjacent the sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material wafer proximate the transistor gate. One of the sidewall spacers extends along the first sidewall of the gate and the other of the sidewall spacers extends along the second sidewall of the gate. The entirety of the semiconductor wafer material under one of the sidewall spacers being defined as a first segment of the semiconductor wafer material, and the entirety of the semiconductor wafer material which is under the other of the sidewall spacers being defined as a second segment of the semiconductor wafer material.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

Abstract: The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a substrate comprising: a) providing a recess in a substrate; b) printing an antenna within the recess; and c) providing an integrated circuit chip and a battery in electrical connection with the antenna.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second trans

Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials.

Abstract: The invention encompasses a living organism sensing device. Such device comprises a conductive loop extending over a substrate. The loop comprises carbon particles. The device further comprises a circuit which includes the conductive loop as a first circuit component and a transponder as a second circuit component. The transponder is configured to emit a first signal if the loop of conductive material is continuous and a second signal if the loop of conductive material is broken. The second signal is different than the first signal. The invention also encompasses a termite sensing device. Such device includes at least one wooden block, and a conductive loop proximate the wooden block. The loop comprises conductive particles of carbon. The termite sensing device further includes an electrical circuit comprising the conductive loop as a first circuit component and a transponder as a second circuit component.