Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: A method of establishing wireless communications between an interrogator and individual ones of multiple wireless identification devices, the method comprising utilizing a tree search method to establish communications without collision between the interrogator and individual ones of the multiple wireless identification devices, a search tree being defined for the tree search method, the tree having multiple levels respectively representing subgroups of the multiple wireless identification devices, the method further comprising starting the tree search at a selectable level of the search tree.

Abstract: A method of establishing wireless communications between an interrogator and individual ones of multiple wireless identification devices, the method comprising utilizing a tree search method to establish communications without collision between the interrogator and individual ones of the multiple wireless identification devices, a search tree being defined for the tree search method, the tree having multiple levels representing subgroups of the multiple wireless identification devices, the number of devices in a subgroup in one level being half of the number of devices in the next higher level, the tree search method employing level skipping wherein at least one level of the tree is skipped.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically a etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: In one aspect, the invention encompasses a LOCOS process. A pad oxide layer is provided over a silicon-comprising substrate. A silicon nitride layer is provided over the pad oxide layer and patterned with the pad oxide layer to form masking blocks. The patterning exposes portions of the silicon-comprising substrate between the masking blocks. The masking blocks comprise sidewalls. Polysilicon is formed along the sidewalls of the masking blocks. Subsequently, the silicon-comprising substrate and polysilicon are oxidized to form field oxide regions proximate the masking blocks. In another aspect, the invention encompasses a semiconductive material structure. Such structure includes a semiconductive material substrate and at least one composite block over the semiconductive material substrate. The composite block comprises a layer of silicon dioxide and a layer of silicon nitride over the layer of silicon dioxide. The silicon nitride and silicon dioxide have coextensive opposing sidewalls.

Abstract: Described is a titanium sputtering target to provide improved step coverage and a method of making same.

Abstract: In one aspect, the invention provides a method of exposing a material from which photoresist cannot be substantially selectively removed utilizing photoresist. In one preferred implementation, a first material from which photoresist cannot be substantially selectively removed is formed over a substrate. At least two different material layers are formed over the first material. Photoresist is deposited over the two layers and an opening formed within the photoresist over an outermost of the two layers. First etching is conducted through the outermost of the two layers within the photoresist opening to outwardly expose an innermost of the two layers and form an exposure opening thereto. After the first etching, photoresist is stripped from the substrate. After the stripping, a second etching is conducted of the innermost of the two layers within the exposure opening.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: The present invention provides methods of transmitting information within a personal handy-phone system wireless local loop and personal handy-phone system wireless local loops. One embodiment of a personal handy-phone system wireless local loop according to the present invention comprises: a base station; a repeater station configured to transmit a plurality of uplink radio signals to the base station and receive a plurality of downlink radio signals from the base station; and a portable station configured to transmit the downlink radio signals to the repeater station and receive the uplink radio signals from the repeater station.

Abstract: The present invention includes methods of increasing the power handling capability of a power line. One method of the present invention includes providing a conductor configured to transmit energy intermediate plural locations; supporting the conductor at a plurality of positions intermediate the locations, the supporting at a plurality of positions defining a plurality of spans of the conductor; creating a model of the conductor; identifying a critical span; altering the modelled conductor responsive to the identifying; and analyzing the modelled an conductor following the altering.

Abstract: The invention encompasses a device for sensing living organisms. Such device comprises a loop of conductive material extending over a substrate, and an insulative protective material over the loop of conductive material. The device further comprises a circuit which includes the conductive material as a first circuit component and which further includes a transponder as a second circuit component. The transponder is configured to emit a first signal if the loop of conductive material is continuous, and a second signal if the loop of conductive material is broken. The invention also encompasses a device for sensing termites. Such device comprises at least two wooden blocks separated by a gap, and a loop of conductive material within the gap. The device further comprises an insulative protective material over the loop of conductive material.

Abstract: The invention encompasses resistors comprising a thin layer of dielectric material and methods of forming such resistors. The invention also encompasses integrated circuitry comprising such resistors, including SRAM circuitry, and encompasses methods of forming such integrated circuitry. In one aspect, the invention includes a resistor construction for electrically connecting a first node location to a second node location comprising: a) a first conductive layer in electrical connection with the first node location; b) a second conductive layer in electrical connection with the second node location; and c) a dielectric material intermediate the first conductive layer and the second conductive layer and having a thickness of from about 15 Angstroms to about 60 Angstroms.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: A new and distinct variety of peach tree denominated varietally as ‘Burpeachone’, and which is characterized as to novelty by producing an attractively colored fruit which is ripe for commercial harvesting and shipment approximately May 17 to May 23 under the ecological conditions prevailing in the San Joaquin Valley of central California.