Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.

Abstract: An antenna circuit configured for use in a radio frequency data communications device has an antenna constructed and arranged to transfer electromagnetic waves, the electromagnetic waves corresponding to a signal carried by the antenna and generated from a signal source. A Schottky diode is electrically coupled in serial relation with the antenna, and in operation the signal is applied serially across the antenna and the diode in direct relation with electromagnetic waves transferred by the antenna. A bias current supply is also electrically coupled to the Schottky diode and is configurable to deliver a desired bias current across the current. The diode is responsive to the bias current to realize a desired diode impedance such that a desired impedance match/mis-match is provided between impedance of the diode and impedance of the antenna when the signal is applied across the antenna circuit, which selectively tunes the antenna circuit by imparting a desired power transfer therein.

Abstract: A capacitor and method for forming a capacitor is disclosed and which includes providing a node to which electrical connection is to be made; forming a first layer of conductive material to a first thickness over and in electrical connection with the node; forming a second layer of insulative material to a second thickness over the first layer, the second thickness being greater than the first thickness; forming a third layer of conductive material to a third thickness over the second layer; forming the first, second and third layers into a first capacitor plate; and forming a capacitor dielectric layer and second capacitor plate operatively adjacent the first capacitor plate.

Abstract: Integrated circuitry having adjacent electrically isolated field effect transistors is disclosed and which includes a bulk semiconductor substrate; an electrically insulative device isolation mass located on the substrate and positioned between opposing active area regions; a first pair of LDD diffusion regions associated with the active area and abutting against the electrically insulative device isolation mass; a pair of field effect transistors each being received within one active area; a second paid of LDD diffusion regions associated with the active area and abutting against each field effect transistor; and a pair of electrically conductive transistor source and drain diffusion regions which are respectively spaced from the insulative isolation mass and field effect transistor.