Abstract: A comminuting apparatus includes a frame, a set of overlapping scissor rolls, a first drive motor, and a second drive motor. The frame has an enclosure with an entrance opening for receiving waste material. The set of overlapping scissor rolls is carried within the enclosure for rotation, including a first scissor roll and a second scissor roll. The first drive motor is coupled to the first scissor roll, and the second drive motor is coupled to the second scissor roll. The first drive motor is operative to drive the first scissor roll at a substantially variable operating speed. The second drive motor is operative to drive the second scissor roll in co-rotation at a substantially constant operating speed.

Abstract: The invention includes a method for forming a ceramic composition. Materials comprising lead, zirconium, titanium and bismuth are combined together to form a mixture. At least one of the materials is provided in the mixture as a nanophase powder. The mixture is then densified to form the ceramic composition. The invention also includes a method for forming a dense ferroelectric ceramic composition. Lead, zirconium, titanium and bismuth are combined together to form a mixture. The mixture is then densified to form a ferroelectric ceramic composition having a density of greater than or equal to 95% of a theoretical maximum density for the composition. A predominate portion of the composition has a grain size of less than or equal to about 500 nanometers. The invention also includes a ferroelectric ceramic composition comprising lead, zirconium, titanium and bismuth.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials.

Abstract: The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling.

Abstract: A dynamic random access memory includes a plate line; a digit line; a memory cell selectively coupled between the digit line and the plate line; sense circuitry selectively coupled to the memory cell to read the memory cell and capable of applying a first voltage from the plate line to the digit line; equilibration circuitry selectively coupling the plate line to an equilibration voltage less than the first voltage and selectively coupling the digit line to the equilibration voltage; and control circuitry configured to cause the equilibration circuitry to couple the plate line to the equilibration voltage while the memory cell is being accessed. A method of manufacturing a dynamic random access memory includes providing control circuitry configured to operate in a specified manner.

Abstract: The invention encompasses methods of forming insulating materials proximate conductive elements. In one aspect, the invention includes a method of forming an insulating material proximate a substrate comprising: a) chemical vapor depositing a first material proximate a substrate; b) forming cavities within the first material; and c) after forming cavities within the first material, transforming at least some of the first material into an insulative second material. In another aspect, the invention includes a method of forming an insulating material proximate a substrate comprising: a) forming porous polysilicon proximate a substrate; and b) transforming at least some of the porous polysilicon into porous silicon dioxide.

Abstract: Methods of forming conductive lines and insulative spacers thereover are described. In accordance with one aspect of the invention, a substrate is provided having a first area and a second area relative to which conductive lines are to be formed. A layer of conductive material is formed over the first and second substrate areas and a layer of insulative material is formed over the conductive material. In a preferred implementation, insulative material is removed from the second area and conductive lines are subsequently patterned and etched in both the first and second areas. In another preferred implementation, conductive lines are first patterned and etched with insulative material in the second area being subsequently removed. The patterned and etched conducted lines have respective sidewalls.

Abstract: In one aspect, the invention encompasses a method of forming an insulating material around a conductive component. A first material is chemical vapor deposited over and around a conductive component. Cavities are formed within the first material. After the cavities are formed, at least some of the first material is transformed into an insulative second material. In another aspect, the invention encompasses a method of forming an insulating material. Polysilicon is deposited proximate a substrate. A porosity of the polysilicon is increased. After the porosity is increased, at least some of the polysilicon is transformed into silicon dioxide.

Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w

Abstract: A stage for a voltage controlled oscillator includes a first p-channel transistor having a gate defining a control node, having a source adapted to be coupled to a supply voltage, and having a drain; a second p-channel transistor having a gate coupled to the control node, having a source coupled to the supply voltage, and having a drain; a first n-channel transistor having a gate defining a first input, having a drain coupled to the drain of the first p-channel transistor and defining a first node, and having a source; a second n-channel transistor having a gate defining a second input, having a drain coupled to the drain of the second p-channel transistor and defining a second node, and having a source; a current draw; first and second loads; a first source follower having an input coupled to the first node; and a second source follower.

Abstract: A wireless communications system comprising a first transponder adapted to be coupled to one of a plurality of selectable antennas, having a look-up table including locations holding data representing antennas, and having pointers pointing to selected ones of the locations, the pointers defining an order in which antennas will be used to attempt communication; and a second transponder configured to communicate with the first transponder, wherein the first transponder uses an antenna defined by data in one location of the table for communication with the second transponder, and, if successful communication with the second transponder is not established, the first transponder uses an antenna defined by data in another location of the table selected in accordance with the order defined by the pointers.

Abstract: Described is the production of a metal article with fine metallurgical structure and texture by a process that includes forging and rolling and control of the forging and rolling conditions. Also described is a metal article with a minimum of statically crystallized grain size and a uniform (100) cubic texture.

Abstract: A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage.

Abstract: Disclosed is a tap driver for rigid tapping, which includes predetermined tension and compression factors to self-synchronize the tap driver. In the preferred embodiment, the tap driver includes helical coils imparted in the tap driver body which allow the attachment body to synchronize axially in response to a force of a predetermined magnitude imparted on the tap. An additional embodiment of this invention provides such a tap driver body wherein the body allows for lateral flexure and movement to compensate for feed error and location error.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation is regions are formed over a semiconductive substrate.

Abstract: A new and distinctive variety of peach tree denominated varietally as Burpeachfour and which is characterized as to novelty by a date of maturity for commercial harvesting and shipment of approximately August 28 to September 8 under the ecological conditions prevailing in the San Joaquin Valley of central California.

Abstract: A new and distinct variety of apple tree (Malus Pumila Mill) named ‘Nevson,’ and which is characterized as to novelty by uniqueness of shape, color, flavor and texture, and a date of maturity for commercial harvesting and shipment of approximately September 10 through October 1 under the ecological conditions prevailing in the Columbia Basin area of Central Washington.

Abstract: A new and distinctive variety of nectarine tree denominated varietally as ‘Burnectone’, and which is characterized as to novelty by a date of maturity for commercial harvesting and shipment of approximately May 25 to June 5, under the ecological conditions prevailing in the San Joaquin Valley of Central California.