Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H-bridge.

Abstract: A replacement for probe cards includes a full wafer contacter. A first surface of the full wafer contacter is brought into contact with, and the contacter is attached to, a wafer, thereby making electrical connection with at least a portion of the contact pads on each of a plurality of integrated circuits on the wafer. The full wafer contacter provides conductive pathways from the IC contact pads to a second surface of the full wafer contacter where a corresponding set of contact pads provide access to test systems and/or other devices. The contact pads on the second surface of the full wafer contacter are typically larger than the contact pads of the integrated circuits, and are typically spaced father apart from each other. The full wafer contacter is constructed to be suitable to provide access to the contact pads of the unsingulated integrated circuits during a wafer burn-in process.

Abstract: A location-aware product includes a location information resource for providing the present location of the location-aware product to within some margin of error, and such present location information is included by the location-aware product in various outputs, including but not limited to, location stamps in files for create, open, and/or modify file operations. In a further aspect, location information may be used in determining the time zone or zones in which one or more operations have occurred, and to provide the basis for updating clocks, or other resources, useful for time stamping of various operations and outputs. In a still further aspect of the present invention, information displays may be sorted by accounting for the differences in times and dates introduced through time stamping of events in different time zones.

Abstract: A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function.

Abstract: Manufacturing and/or operational variations that affect performance of an integrated circuit (IC) are at least partially compensated for, by determining the magnitude of these variations and providing one or more corresponding control signals to a voltage regulator, which, responsive thereto, increases or decreases the magnitude of the output voltage. The output voltage of the voltage regulator is typically provided to a power supply node of the IC. Similarly, the output of the voltage regulator may be provided to a substrate portion of the IC, so as to provide a substrate bias that is variable in response to changes in the performance of the IC.

Abstract: Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors.

Abstract: Coax and twinax connector assemblies, suitable for low-cost manufacturing and high-frequency performance, include one or more slices of insulating material having a series of through-holes therein. Dimensions of the through-holes are tailored to the dimensions of the coax or twinax that are to be fitted to such connector assemblies. The slices may have dimensions that are uniform to within typical manufacturing tolerances. By combining, or stacking, the slices, the connector height can be customized to a particular application. A variety of slice thicknesses are provided so that a variety of final connector heights may be achieved. Conductive material sheets may be disposed between one or more pairs of connector slices so as to provide a common ground connection for one or more conductors, such as, for example, ground shields, disposed in the through-holes of the stacked connector slices. Additionally, right angle connectors and low-cost twinax cables are disclosed.