Patents Represented by Attorney Westernman, Hattori, Daniels & Adrian, LLP.
  • Patent number: 7583157
    Abstract: A method of manufacturing a temperature compensated oscillator including the steps of assembling an oscillator in which an IC chip constituting a temperature compensation circuit with an oscillation circuit and a compensation data storage circuit, and a resonator for the oscillation circuit are mounted in a package; adjusting the resonator with an oscillation frequency of the oscillation circuit to a desired oscillation frequency in condition that the oscillator is kept at a reference temperature, in condition that a temperature compensation function of the temperature compensation circuit is disabled; sealing the resonator hermetically; creating temperature compensation data and storing it into the compensation data storage circuit; and enabling the temperature compensation function of the temperature compensation circuit.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 1, 2009
    Assignee: Citizen Holdings Co., Ltd.
    Inventor: Yasuhiro Sakurai
  • Patent number: 7579507
    Abstract: Crystals of a salt of 4?-{2-[(1S,2R)-2-hydroxy-2-(4-hydroxyphenyl)-1-methylethylamino]ethoxy}-3-isopropyl-3?,5?-dimethylbiphenyl-4-carboxylic acid. The ? type, ? type and ? type crystals produced by treating hydrochloride of 4?-{2-[(1S,2R)-2-hydroxy-2-(4-hydroxyphenyl)-1-methylethylamino]ethoxy}-3-isopropyl-3?,5?-dimethylbiphenyl-4-carboxylic acid with specified solvents, which can be discriminated by the characteristic diffraction peaks of powder X-ray diffractometry and the like.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: August 25, 2009
    Assignee: Kissei Pharmaceutical Co., Ltd.
    Inventors: Kiyoshi Kasai, Takehiro Ishikawa, Tetsuji Ozawa, Koji Kamata, Ritsu Suzuki, Hideki Takeuchi
  • Patent number: 7378352
    Abstract: After low dielectric constant films are formed on a wiring, hardmasks are formed on the low dielectric constant films. A resistmask is formed on the hardmasks. Via holes are formed in the low dielectric constant films using the resistmask. Ashing the resistmask is performed. During this process, a protection film is formed by sticking a sputtered material generated from the resistmask at least onto side surfaces of the via holes. Thereafter, the via holes are extended to the wiring, and a conductive material is buried into the via holes.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: May 27, 2008
    Assignee: Fujitsu Limited
    Inventor: Yoshihisa Iba
  • Patent number: 7361980
    Abstract: A semiconductor device comprises a semiconductor chip in which a circuit part provided in a center of the semiconductor chip is connected with power-supply lines and power-supply electrodes to supply power from an external power source to the circuit part. A substrate is provided for carrying the semiconductor chip thereon and provided so that first terminals in a region encircling the semiconductor chip are electrically connected to the power-supply electrodes. A first opening is formed on the power-supply line in a center of the circuit part. A second opening is formed on the power-supply line at a peripheral part of the circuit part. A conductor layer is electrically connected to second terminals in the region encircling the semiconductor chip on the substrate, and provided so that the power-supply line in the first opening and the power-supply line in the second opening are connected together.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 22, 2008
    Assignee: Fujitsu Limited
    Inventors: Sumikazu Hosoyamada, Kazuto Tsuji, Yoshihiro Kubota
  • Patent number: 7109128
    Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: September 19, 2006
    Assignee: Fujitsu Limited
    Inventors: Koichi Sugiyama, Yoshihiro Takao, Shinji Sugatani, Daisuke Matsunaga, Takayuki Wada, Tohru Fujita, Hikaru Kokura
  • Patent number: D576544
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: September 9, 2008
    Assignee: Toyo Tire & Rubber Co., Ltd.
    Inventor: Mitsunobu Onoe
  • Patent number: D584658
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: January 13, 2009
    Assignee: Honda Motor Co., Ltd.
    Inventor: Toshinobu Minami