Abstract: An improved packaging scheme for a CPU of a main frame computer improves the performance while at the same reduces the cost of manufacture of the main frame computer. A single packaging technology is used to package the whole CPU and eliminates cable connections inside the CPU. Surface power bus technology permits the fabrication of a module with chips mounted on both front and back sides of the substrate. The surface power bus is installed on one or both sides of the module surface and derives power directly from the power cable and distributes power to chip sites directly. In a specific implementation, a uni-processor CPU with chips mounted on both surfaces of the substrate and power fed from the surface power bus results in improved processor package density and system performance.

Abstract: A power semiconductor assembly, particularly a semiconductor switch assembly which has a number of discrete emitter connection pads, comprised of a metal matrix composite housing and a copper or aluminum post with a cross-sectional area sufficiently large to carry the rated current providing a single-point, external connection to all emitter pads. The post passes through and is supported by an insulating ceramic insert such as aluminum oxide in the wall of the metal matrix composite housing. The post is hollowed out in the region where it passes through the ceramic insert in order to reduce the mechanical stress between the post and the insulating insert as a result of the mismatch in their thermal expansion coefficients. Buses on either side of the semiconductor die provide surfaces for connection from the post to the discrete emitter connection pads on the die.

Abstract: An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory).

Abstract: A microcomputer includes a maskable interrupt request terminal, a maskable interrupt request terminal, and a nonmaskable interrupt request terminal, and internally contains a status register having a group of flags indicating a maskable interrupt allowing level, a flag indicating that a nonmaskable interrupt processing is under execution, a flag indicating that an exception processing is under execution, and a flag indicating inhibition of the maskable interrupt. There are also internally provided first and second save registers for saving the content of the status register and the content of a program counter, respectively, when the maskable interrupt request is acknowledged, and third and fourth save registers for saving the content of the status register and the content of a program counter, respectively, when the nonmaskable interrupt request is acknowledged.

Abstract: A probe 100 which can be formed from a molded plastic provides an inexpensive construction for a probe which may be readily replaced in electrical testing apparatus, particularly of the automated type. A conductive contact tip 18 is preferably co-molded into a cantilevered portion 14' of a body block 14 and a conductive material 16 is provided over a portion of the surface of the body block 14 extending from the contact tip 18 to an attachment portion 15 of the body block. Cooperating attachment structures 22, 24 are provided on both the body block 14 and a holder block 20 to provide a snap fit therebetween. The holder block 20 can be provided with a resilient tab 29 opposing the attachment portion of the body block for engagement with a connector lug 12 of the testing apparatus, sandwiching the connector lug 12 between the attachment portion 15 of the body block 14 and the holder block 20. Flanges of the holder block 20 provide lateral support for the cantilevered portion 14' of the body block.

Abstract: A six-stage pipeline processor comprised of the sequential stages: instruction fetch; instruction decode; first full ALU; second full ALU; Fill Register; and Write Back Register. Memory addresses are calculated in the first ALU stage and this stage presents the address along with a read command to memory at the end of the cycle. Two cycles are allowed for a data response from memory but only one intervening instruction is required to occupy the pipeline for most instruction sequences because bypass logic makes available data operands from memory at the second ALU stage with an apparent load latency of one cycle. Subtraction and other arithmetic operations are performed in the first ALU if the result is to be used by a subsequent LOAD instruction to calculate a memory address so that the result can be used by the first ALU to calculate the memory address without any intervening instruction and potential loss of overall performance.

Abstract: Apparatus for plasma processing involving the gettering of particles having a high charge to mass ratio away from a semiconductor wafer are disclosed. In one aspect of the invention, magnets are used to produce a magnetic field which is transverse to an electric field to draw the negative particles away from the wafer to prevent the formation of a sheath which can trap the particles. In a second aspect of the invention, a power source is connected to the wafer electrode to maintain a negative charge on the wafer, thereby preventing negative particles from being drawn to the wafer surface when the plasma is turned off. In other embodiments of the invention, a low density plasma source is used to produce a large plasma sheath which permits particles to cross a chamber to be gettered. A low density plasma discharge followed by a pulse to a higher density is used to overcome the negative effect of an insulating layer between the wafer and the wafer electrode.

Abstract: A single crystal pulling apparatus of the Czochralski method type wherein the cylindrical heater is supported not only by the two existing electrodes which are vertically shiftable but also by one or more vertical shafts, which may be electrodes or electrically insulated dummy electrodes; the vertical shafts are capable of shifting vertically in synchronism with the existing two electrodes, and are arranged in a manner such that the existing two electrodes and the vertical shafts are at regular intervals along the bottom circumference of the cylindrical heater.

Abstract: A three-phase, pulse-width-modulated, switching rectifier, with zero-voltage-switching.

Abstract: Improved cellulosic beads for use as supports in bioaffinity chromatography are produced by dissolution of cellulose in a chaotropic cellulose solvent, formation of the dissolved cellulose into droplets, and immersion of the droplets into a non-solvent capable of solvent interchange with the cellulose solvent to form generally spherical porous cellulose beads of narrow particle size distribution. The beads formed are preferably made with cellulose having a degree of polymerization between 100 and 200, and the resulting beads when saturated with water without drying contain between 1% and 7% cellulose by weight and have a particle size of at least about 0.3 mm. The beads can be activated by a suitable activation method, and specific bioaffinity ligands are bound to the active sites in the beads. The beads reacted ligands, the beads then used in bioaffinity chromatography to isolate specific bioaffinity molecules having molecular weights between 5,000 and 500,000 from complex solutions.

Abstract: A macroservice engine is provided to exclusively carry out a sequence control in a processing of a macroservice. On the other hand, a command execution unit carries out no macroservice, but generates a bus cycle exciting request for a bus control unit, when an access request signal is generated to access a memory or peripheral registers included in a microcomputer. Thus, a processing of interruption is carried out with high speed, and a burden of a central processing unit is relieved in an interruption process.

Abstract: A microprocessor which prefetches instructions in words which contain a fixed plurality of bytes based on addresses which disregard one or more less significant bits and in which instructions comprises a variable number of bytes includes an adder for supplying information regarding the starting location for each instruction within a multi-byte, prefetched word held in a queue for alignment of the instruction for decoding by an instruction decoder. Upon the occurrence of an unconditional branch instruction or a conditional branch instruction in which the condition is met, a multiplexer is used to substitute a starting location stored in a branch hit table for the branch target instruction within a multi-byte, prefetched word for the starting for the starting location developed by the adder.

Abstract: Extrusion method and apparatus in which the liquid precursor of the extruded material is forced through a die formed by two surfaces moving in opposite directions relative to one another and transversely to the direction of material flow. Immediately upon exiting this dynamic die, the extracted material is removed as a sheet or film through a take-off system. In a preferred embodiment of the invention, the first die is formed by members rotating on a common axis in opposite rotational directions.

Abstract: An isolated zero-voltage-switching converter in which the magnetizing inductance of the isolating transformer is a resonant element and an open circuit is provided on the secondary side of the transformer during the time interval when both primary switches are off. When the secondary of the transformer is open, the magnetizing inductance is in series with the capacitances of the primary switches, thus forming a resonant circuit.

Abstract: When DMA transfer for a DMA transfer area is completed, DMA transfer for the next area may be continuously executed or stopped. In addition to this, if there is a need to urgently stop DMA transfer being executed, DMA transfer can be immediately stopped without waiting for the end of DMA transfer currently executed. For continuous DMA transfer for a plurality of DMA transfer areas, the device may be provided with an authorization bit to authorize DMA transfer operation and a next area authorization bit to authorize DMA transfer for the next area and the contents in the next area authorization bit are set to the DMA authorization bit when the terminal counter which counts the number of DMA transfer data reaches the predetermined value due to decrement. Depending on the contents in the DMA authorization bit, DMA transfer may be continued or stopped when the next DMA transfer request is generated.

Abstract: A parallel multiplication circuit includes a plurality of Booth's decoders, a plurality of partial product generation circuits, and a plurality of full adders. Each Booth's decoder is constructed in accordance with the following decode signal generating logic:T.sub.w =Y.sub.i .sym.Y.sub.i-1P.sub.u =Y.sub.i+1Z=Y.sub.i+1 .sym.Y.sub.i .multidot.Y.sub.i .sym.Y.sub.i-1Each partial product generation circuit is constructed in accordance with the following partial product generating logic:PP=(T.sub.w .multidot.X.sub.i +T.sub.w .multidot.X.sub.i-1).sym.P.sub.

Abstract: A high density array of pinless electrical, spring connectors are supported in an electrically insulative carrier. The carrier has an array of cavity nests for receiving the spring connectors, locking them into a stable position and functioning as an electrical coupler between corresponding electrical contact pads in stacked modules.

Abstract: An integrated tip strain sensor is combination with a single axis atomic force microscope (AFM) for determining the profile of a surface in three dimensions. A cantilever beam carries an integrated tip stem on which is deposited a piezoelectric film strain sensor. A high-resolution direct electron beam (e-beam) deposition process is used to grow a sharp tip onto the silicon (Si) cantilever structure. The direct e-beam deposition process permits the controllable fabrication of high-aspect ratio, nanometer-scale tip structures. A piezoelectric jacket with four superimposed elements is deposited on the tip stem. The piezoelectric sensors function in a plane perpendicular to that of a probe in the AFM; that is, any tip contact with the linewidth surface will cause tip deflection with a corresponding proportional electrical signal output. This tip strain sensor, coupled to a standard single axis AFM tip, allows for three-dimensional metrology with a much simpler approach while avoiding catastrophic tip "crashes".

Abstract: In a pseudo random pattern generation circuit having a normal input operation mode, a boundary scanning operation mode and an inherent pseudo random pattern generation mode, output stage selectors are provided to supply input data as output data without modification in the normal input operation mode. In addition, flipflops are provided to hold the data in the boundary scanning operation mode, so that the data held in the flipflops are not supplied as output signals. Thus, in the normal input operation mode, the data processing speed is increased, and in the boundary scanning operation mode, the data just before the boundary scanning operation mode is maintained without being outputted to an internal circuit of the LSI chip.

Abstract: A serial interface circuit for performing operations in a plurality of modes is disclosed, which includes an input terminal supplied with a serial data, a first shift register fetching and shifting data at the input terminal in synchronism with a clock signal, a selector for selecting the input terminal in a first mode and an output of the first shift register in a second mode, a second shift register fetching and shifting data at an output of the selector, a set of first output terminals, a set of second output terminals, and an output control circuit outputting first data derived in parallel from the first shift register and second data derived in parallel from the second shift register to the first and second output terminals in the second mode and one of the first and second data to one of the first and second output terminals in the first mode. The respective operations in the first and second modes are thus performed. The output control is favorably incorporated with a bit order reversing function.