Abstract: An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.