Patents Represented by Attorney Whitham, Curtis, Whithan & McGinn

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  • Glitch-free dual clok read circuit
    Patent number: 5606526
    Abstract: A dual clock Read circuit for a memory array having a first latch that is set in response to a data ready signal and a second latch that is set in response to a first clock signal. Logic circuitry generates a second clock signal when the first and second latches are set. A third latch is set in response to the second clock signal for latching the data from the memory array before it is forwarded to an off-chip driver.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: February 25, 1997
    Assignee: International Business Machines Corporation
    Inventor: Harold Pilo