Abstract: A cache memory apparatus to be coupled to a main memory, comprises a cache memory having a plurality of ports and capable of being independently accessed through the plurality of ports. The cache memory stores a portion of data stored in the main memory and tag information indicating memory locations within the main memory of the data portion stored in the cache memory. A hit discriminator receives first tag information included in an address given when the cache memory is accessed and second tag information read from the cache memory in accordance with the given address, in order to discriminate a cache-hitting and a cache-missing on the basis of the first and second tag information. A replacement control circuit operates for replacing data and corresponding tag information in the cache memory when the cache-missing is discriminated by the hit discriminating circuit.