Abstract: A computer case shaped to provide cooling of the computer's electronic parts is described. The case is formed from metal or thin plastic which can be stamped or injection molded in the desired shape for cooling. The case has a plurality of sides and a bottom. In a first aspect, a plurality of ribs is formed on at least one of the sides, thereby increasing the surface area available for heat dissipation. The bottom may also be corrugated. In a second aspect, slots are provided in at least one of the sides, and the heat generating microprocessor is positioned adjacent to the slotted sides. In a third aspect, a plate is attached to the bottom by means of angled edges at the periphery of the plate so as to allow a gap between the attached plate and the case bottom for trapping a gas therebetween and providing insulation from heat at the case bottom. Optionally, openings are provided in the angled edges for additional convective cooling of the case bottom.

Abstract: A WDM optical circuit includes an optical circulator having a first path from a first port to a second port and a second path from the second port to a third port. The optical WDM signals received from the second port of the optical circulator are separated out by a WDM coupler on wavelengths, respectively. One of the optical signals on a selected wavelength is dropped and a new signal is added on the same wavelength by an optical transceiver.

Abstract: A planarizing system which significantly reduces the problems associated with non-uniform removal of surface material across the face of a semiconductor wafer or other comparable workpiece. The invention involves a planarizing apparatus that takes the leading edge of a wafer out of contact with the polishing pad while concomitantly enhancing slurry penetration and distribution at the polishing pad-wafer interface. This result is accomplished by combining: means for deflecting upward a portion of a flexible polishing pad as it passes in rotation beneath a wafer to form a raised polishing pad area, and means for positioning the wafer such that the wafer's leading edge overhangs the front edge of the raised polishing pad area during the planarization procedure. The invention also encompasses a method of using the planarizing apparatus to uniformly remove surface material across the face of a wafer.

Abstract: In an ink jet printer, a belt-type preheating unit 2 pressingly heats a recording sheet 6 while transporting the recording sheet in a transport direction B on a belt. A suction transport device 3 is positioned downstream of the belt-type preheating unit 2 in the transport direction B. The suction transport means transports, on its transport belt, the recording sheet 6 heated by the belt-type preheating unit 2 in the transport direction B while fixing the recording sheet onto the transport belt by a vacuum suction. An ink jet print head, positioned confronting the suction transport device 3, records images by ejecting water-based ink onto the recording sheet which is being transported by the suction transport device.

Abstract: There is provided a semiconductor integrated circuit device including an external source voltage detector for keeping transmitting a first signal after detecting that an absolute value of external source voltage provided externally of the semiconductor integrated circuit device has exceeded a first threshold voltage, and an internal source voltage generator for generating a constant internal source voltage regardless of the external source voltage while the absolute value of the external source voltage is in a predetermined range, and providing the external source voltage as it is as an internal source voltage while the first signal is being kept transmitted. The semiconductor integrated circuit device makes it possible to externally control an internal source voltage to be applied to an internal circuit mounted in an IC chip without addition of control terminals over a wide range of an external source voltage.

Abstract: A method and apparatus for processing sheets, includes placing a sheet on a carrier to form a sheet/carrier structure, sizing the sheet/carrier structure, stacking the sheet/carrier structure in a stacking apparatus having a second sheet stacked in advance therein, so that the sheet contacts the second sheet, aligning the sheets with pins, tacking the sheet to the second sheet and removing the carrier.

Abstract: A process for manufacturing a semiconductor device includes defining chip sections on a wafer by scribe lines with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for on the chip electrodes. Aluminum interconnection layers are provided such that each layer is connected to the chip electrode at one end thereof and the other end of the layer is extended towards the central portion of the chip section. A cover coating film is applied on the passivating film and the layers. A number of apertures are formed in the coating film passing therethrough, and bump electrodes are formed at the position corresponding to the apertures. The chip sections are then separated from each other along the scribe lines into semiconductor devices.

Abstract: A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.

Abstract: In a portable telephone apparatus selectively operable in a portable mode or in an on-board mode, an option circuit is built in a chargeable battery pack for adding an extra function to a telephone. A plurality of keys are arranged on the telephone and operable to cause the telephone and option circuit to interchange speech signals and control signals and to start and stop operating.

Abstract: A driver circuit for a liquid crystal display device has an output terminal, an N-MOS transistor, a P-MOS transistor, a first semiconductor switch connected between the output terminal and the N-MOS transistor and, a second semiconductor switch connected between the output terminal and the P-MOS transistor. Each of the N-MOS transistor and the P-MOS transistor have source, drain, gate and substrate, and form a power source portion taking the source as an output side. The first and second semiconductor switches have control inputting means for inputting a switching control signal for alternately outputting the output voltages of the N-MOS transistor and the P-MOS transistor through the output terminal. The drain, gate and substrate voltages are set so that the output voltage output from the N-MOS transistor is greater than the output voltage output from said P-MOS transistor.

Abstract: The present invention relates to a method and apparatus for the handling of rods such as drilling rods, roof bolts, or rib bolts, so that they can be removed directly from a storage cradle near a drilling rig or other mining operation machinery. The invention removes the need to manually load rods into drill rigs or other machinery, by a system of transportation mechanisms made up of straps and/or hydraulic actuators, and gate mechanisms to control the entry and exit of the rods from a storage cradle. Gripping mechanisms are also included to deposit the rods to and from a desired location on the drill rigs or other machinery.

Abstract: A timing signal generator of an MPEG video decoder is responsive to a picture type signal for selectively generating one of a timing signal for decoding I and P pictures and a timing signal for decoding a B picture within a predetermined period of time, permitting an increased speed for the B picture decoding.

Abstract: A shift register constituting a scanning pass test circuit is divided into a plurality of groups, and bypass selectors are inserted into the divided positions of the shift register. A latch circuit is connected to each of the clock signal terminals of the flip-flop circuits which are disposed at the first stage of the flip-flop circuit groups.

Abstract: A polyalkylmethacrylate co-polymer of polyhydroxystyrene has been found to be an ideal blending partner in a novolak photoresist composition. The preferred co-polymer is poly(p-hydroxystyrene)-co-(methyl methacrylate). The co-polymer is fully miscible with novolaks and has a high thermal stability (>150.degree. C.).

Abstract: Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.

Abstract: A portable calculator for operating a calculation between arrays or between an array and a single operand has an array detecting section. The array detecting section identifies each of operands included in an arithmetic expression as a single operand or an element of an array including a plurality of elements, each successive two of elements in the array sandwiching a space and sandwiching no operator. The calculation is executed defined by the arithmetic expression between each of the elements of a single array and a single operand or between corresponding elements of a plurality of arrays.

Abstract: A multiprocessor system includes first and second microcomputers, a address decoding mechanism, and a ready signalling device. The address decoder is coupled to an address bus, to decode address information transferred by the second microcomputer, and supplies a request signal to a request signal input terminal of the first microcomputer. A bus control unit of the first microcomputer responds to the request signal to detect whether an internal bus of the first microcomputer is free from being used by the CPU, and outputs an acknowledge signal to an acknowledge signal output terminal when the internal bus is free. The ready signaling device is coupled to the acknowledge signal output terminal to supply the ready signal to a ready signal input terminal of the second microcomputer in response to the acknowledge signal outputted at the acknowledge signal output terminal and the request signal.

Abstract: Data communication equipment incorporating a matrix switch 11 and a control section 19 in which the matrix switch 11 is provided between M terminal interface units 12.sub.1 -12.sub.M and N communication channel interface units 13.sub.1 -13.sub.N and is capable of switching the combination of the N communication channels 10.sub.1 -10.sub.N and the M data terminal units 18.sub.1 -18.sub.M to enable mutual connections between a desired pair of communication channel and interface units. The controller 19 controls the matrix switch 11 and prescribes the appropriate connections between one of the N communication channel interface units 13.sub.1 -13.sub.N and one of the M terminal interface units 12.sub.1 -12.sub.M. Both the N communication channel interface units 13.sub.1 -13.sub.N and the M terminal interface units 12.sub.1 -12.sub.M are capable of inserting or extracting the connections to the matrix switch 11 on a unit-to-unit basis by means of a pair of N terminal groups 15.sub.1 -15.sub.

Abstract: A multi-prediction branch prediction mechanism predicts each conditional branch at least twice, first during the instruction-fetch phase of the pipeline and then again during the decode phase of the pipeline. The mechanism uses at least two different branch prediction mechanisms, each a separate and independent mechanism from the other. A set of rules are used to resolve those instances as to when the predictions differ.