Abstract: The multiplexing character processor of the present invention multiplexes data characters to and from a plurality of communication lines to a Central Processing Unit by bit slicing. Input data present on the plurality of communication lines is sampled at a rate which is at least 16 times the data bit rate and is formulated as a serial data bit stream. Each sample corresponds to a time slice which slice is allocated to a given communication line under the control of a scan list. A high data rate communication line can be placed on the scan list more than once to insure accurate data reproduction. Character assembly and disassembly is performed in an arithmetic logic unit (ALU) under program control, to provide the flexibility to support various communication link protocols. The input data on each communication line may have a different protocol. Synchronization of the serial data bits to the communication lines is performed by a data bit synchronizer DBS.

Abstract: An electronic business machine having a cash drawer therein, the electronic business machine including a circuit which operatively couples the microprocessor to a driver which energizes a device, such as a solenoid, for a predetermined period of time, which can be altered by programming, in order to open the cash drawer. An alternative embodiment discloses a multivibrator being used in place of the circuit for energizing the driver.

Abstract: A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.

Abstract: An arbitration circuit especially useful for SCSI-II applications, but also having other applications. The basic arbitration circuit requires only thirty NOR gates, one inverter, and connection to all but the lowest priority data line in order to have an arbitration circuit for sixteen lines. The basic circuit will arbitrate among up to sixteen units and is extremely compact and could be used on SCSI related integrated circuits in addition to other SCSI circuitry. The basic arbitration apparatus may also be expanded to accommodate a thirty-two line SCSI-II bus by extending the number of stages to thirty-two.

Abstract: A printed circuit board backpanel uses stripline construction to allow emitter coupled logic. (ECL) signals and transistor-transistor logic (TTL) signals on the same signal layer, while providing electromagnetic interference (EMI) emission control.

Abstract: An automatic paper feed apparatus includes a receptacle for a paper roll, which receptacle comprises a curved floor and opposite side walls which slope outwardly from bottom to top. The floor is ribbed on it sinner surface to minimize frictional engagement of a leader from the paper roll with said floor. Within the receptacle, the paper roll rests upon a guide roll and a first feed roll which is capable of rotating the paper roll to feed a paper web from the roll. A guide chute is provided which guides movement of the paper web from the paper roll to an exit portion of the guide chute from where it may be introduced into a printer or other device. The guide chute is comprised of a portion of the floor of the receptacle and a movable upper element. The movable upper element is pivotally mounted at one end on the shaft associated with the first feed roll.

Abstract: A scanning system having a laser and a motor for spinning an optical mirror arrangement for sensing indicia such as bar codes is capable of turning off the laser and the motor during periods of extended inactivity in order to minimize wear of these components and to reduce the use of electricity. Changes in the ambient light level adjacent to the scanning system which are typical of human motion are detected and are used to produce an electrical signal which can be used to turn the laser and the motor back on.

Abstract: A file backup system for POS data includes a master terminal and a backup terminal along with a master file and a backup file, all of which are coupled to a plurality of satellite terminals. A file controller is provided for each of the files. When one of the files is down, the master file is capable of copying the contents of the down file while simultaneously responding to a request from any terminal and controlling the transfer of data without stopping the operation of the system.

Abstract: A communication system uses a two-wire circuit and includes a master terminal and a backup terminal, and a main file and a backup file along with associated link control devices coupled to a plurality of satellite terminals. Each link control device functions both as a monitor and as a communication controller with priority between the link control devices for each of the files and terminals to maintain operation of the system.

Abstract: A detector assembly for use in an optical reader comprises a hollow housing in which is mounted on the central axis of the housing a collection lens, a routing mirror, a light filter and a photodetector. A routing lens mounted in the side of the housing and on an axis which is perpendicular to the central axis of the housing directs the scanning light at the routing mirror which in turn reflects the light in a scanning direction.

Abstract: A document sensing apparatus includes a phototransistor (12) for generating a first or second voltage depending on whether or not, respectively, a document is present at a sensing location, and a capacitor (36) for providing a second voltage whose peak value is determined by said second value. A voltage comparator (30, 38, 40) compares said first and second voltages and provides an output signal indicative of the presence of a document at the sensing location if said first voltage is less than a predetermined fraction of said second voltage. A microprocessor (44) controls the operation of a circuit (71-1) which provides, as necessary, a charging current to said capacitor (36) so that, while a document is present at the sensing location, said second voltage is prevented from falling by a significant amount, thereby preventing problems occurring if a document remains at the sensing location for a prolonged period due to a feeding irregularity.

Abstract: A device and method for generating a symmetrical clock signal. The device comprises a signal generator, buffer and differential amplifier. The signal generator generates a periodic wave signal. The buffer receives the periodic wave signal and provides a square wave clock signal. The differential amplifier receives the clock signal and a reference voltage signal and provides an error signal to the buffer.

Abstract: A computer monitoring device for recording the number of times address locations of a computer are accessed by a test program in order to determine if each available address is addressed by the test program and the frequency of the accesses. Omissions or low numbers of accesses reveal weak portions of the test program. The device is comprised of a probe for coupling to the address bus of the computer under test, a monitor computer and an address analyzer coupled to the probe and the monitor computer. The analyzer is comprised of a memory having at least one addressable location for every valid address that appears on the address bus. For each address received a fetch of a count stored at the location represented by that memory address is performed and the count is incremented by one and stored back into the memory at the accessed location.

Abstract: In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Abstract: A self-aligning inking roll for a printer which includes an inking roll, an ink transfer roll, a printer, and an endless ribbon mounted on the transfer roll and the printer so as to provide a fresh supply of ink thereto. The inking roll is mounted on an aligner member which is mounted on a support member, with the support member being mounted on an arm which is resiliently biased towards the transfer roll. The aligner member is mounted on the support member at the midpoint of the aligner member so as to provide a fulcrum area which enables the aligner member with the inking roll thereon to pivot and thereby establish a line contact with the transfer roll with the ribbon thereon.

Abstract: A data synchronizer that operates at two to four times greater clock and data rates than previous data synchronizers. By using a positive feedback, self latching gate as the first memory element, rather than a cross-coupled device such as a flip-flop, such rates are attained without inducing metastable oscillation. The positive feedback, self latching gate is far less prone to metastable oscillation since it does not have two cross-coupled devices fighting each other to resolve the proper response to an input. Instead, the self latching gate latches up if a data HIGH is present during a clock HIGH, and remains LOW otherwise. External circuitry resets the self latching gate to the LOW state before the start of each clock HIGH cycle to remove any previous latched state. The self latching gate output is then synchronously sampled by a type D flip-flop to provide a completely synchronized data output.

Abstract: A converter circuit for converting binary logic signals from a CMOS circuit into binary signals for an ECL circuit. Two output transistors in the converter circuit are connected in parallel between the V.sub.DD CMOS supply voltage and the output of the converter circuit. The resistance across the drain-to-source terminals of the output transistors form a voltage divider network with a pulldown resistor in the ECL circuit. In one embodiment, one of the output transistors is enabled by a logic "1" from the CMOS circuit and the other is enabled only by a logic "0". In another embodiment, one output transistor is always enabled and the other is enabled only by a logic "0" from the CMOS circuit. In both embodiments, the effective resistance across the parallel transistors is different for a logic level "1" and a logic level "0", so that the voltage at the output is also different.

Abstract: A magnetic thermal transfer ribbon includes a substrate and a thermal sensitive coating which is a mixture and essentially consists of a fatty alcohol, a water base latex, an intensifying dye, an adhesive, and a surface agent along with iron oxide, and the coating mixture is dispersed in alcohol, in water, or in a combined water/alcohol mixture.