Abstract: An exemplary embodiment of the invention is a virtual memory structure having a first virtual memory space and a virtual page frame table space. The first virtual memory space includes at least one private area and at least one common area. The virtual page frame table space is separate from the first virtual memory space. The virtual page frame table space includes at least one page frame table entry representing a frame of real memory.

Abstract: An exemplary embodiment of the invention is an interconnection system including a primary connector having a first detection contact coupled to a first voltage, a second detection contact coupled to said first voltage and a reference contact coupled to a second voltage. The interconnection system includes a secondary connector having a first contact, a second contact and a secondary reference contact. The second contact and secondary reference contact are electrically connected. The first contact makes electrical connection with the first detection contact, the second contact makes electrical connection with the second detection contact and the secondary reference contact makes electrical connection with the reference contact. When the second detection contact makes electrical connection with the second contact, the second detection contact is connected to the second voltage.

Abstract: A digital signature system that employs a temporary digital ID signed by using a private key, so that the digital ID can be used as a proxy for a specific period of time and for a specific purpose. When a signature is requested by a server application, a user does not use his or her private key, but employs a temporary key generated using the private key. A temporary certificate for the temporary key is signed using the user's private key. The temporary certificate includes information concerning the period of time during which the temporary certificate is valid and information concerning the purpose for which used. Upon receipt of a request from an application that a document be signed, a client transmits to the server a document signed using the temporary key, the temporary certificate and a user's certificate. First, the server examines the signature; second, it determines whether the temporary certificate is still effective, i.e.

Abstract: A method and apparatus, operating within a kernel of a UNIX-based host computer, that ensures that no unauthorized users or processes have accessed a pseudo-terminal (pty) slave file within a pty device driver prior to an authorized process accessing the pty slave file. Specifically, upon receiving, from an application program, a request to open a pty master file to form a pty device driver, the request is granted by the kernel only if the pty master file and pty slave file are presently closed. Similarly, a request to open a pty slave file to form a pty device driver is granted by the kernel only if the pty master file is open and a user identification of an application attempting to open the slave file is identical to a user identification of the application program which opened the master file. In this manner, a pseudo-terminal link between the pty master file and the pty slave file is secure from unauthorized processes being surreptitiously connected to the pty slave.

Abstract: In a data base system management system having a dictionary for maintaining a list of sets of data associated with each of a plurality of user application programs, a method and apparatus for decreasing the data base access time by forming a data model of the logical relationship of said list, generating static access modules, creating a secondary data model in a pre-built machine executable format and storing the data model. In the execution stage accessing the secondary data model and manipulating data values using the secondary data model.

Abstract: A heat-conductive honeycomb ceramic spacer having an array of apertures for facilitating assembly of a semiconductor device including a plurality of semiconductor stacks using a low-profile contact comprising a foil with raised portions corresponding to the locations of apertures in the ceramic spacer for forming contacts with the semiconductor stacks when the spacer and the stacks are sandwiched between the foil and another conductive sheet. Use of such a foil also allows disconnection of defective stacks in the device. Extra stacks are provided to compensate for defective stacks, according to an n-x design philosophy. Solder preforms may be included on the stacks and enhanced connections made to the foil of conductive sheet by causing reflux of the solder preforms. The invention may also be applied to multi-layer device constructions.

Abstract: A system and method for preventing deadlock in a multiprocessor computer system executing instructions requiring multiple resources. The system detects potential deadlock situations where a multi-resource instruction is blocked from obtaining one of the resources. A multi-resource instruction global lock is provided that can be held by at most one processor. Upon conflict detection, the processor attempts to acquire the multi-resource instruction global lock and, if successful, resumes resource acquisition. The use of a global lock serializes multiple resource requests and assures that the processor holding the lock can eventually acquire all required resources without deadlock with another processor. The preferred embodiment acquires the global lock on an exception basis to minimize the overhead impact. However, an alternate embodiment which uses the global lock in each multiple resource instruction could also be implemented.

Abstract: A task scheduler for use in a multiprocessor, multitasking system in which a plurality of processor complexes, each containing one or more processors, concurrently execute tasks into which jobs such as database queries are divided. A desired level of concurrent task activity, such as the maximum number of tasks that can be executed concurrently without queuing of tasks, is defined for each processor complex. Each job is assigned a weight in accordance with the external priority accorded to the job. For each job there is defined a desired level of concurrent; task activity that is proportional to its share of the total weight assigned to all concurrently executing jobs. The jobs are prioritized for execution of awaiting tasks in accordance with the discrepancy between the desired level of multitasking activity and the actual level of multitasking activity for each job.

Abstract: The invention described herein suggests methods of cryptographic key management based on control vectors in which the control vectors are generated or derived internal to a cryptographic facility implementing a set of cryptographic operations. The methods of alternate control vector enforcement described in the present application provide a high-integrity facility to ensure that cryptographic keys are used in a manner consistent with the type and usage attributes assigned to the keys by the originator of those keys. Since the control vectors are generated or derived internal to the cryptographic facility on the basis of data contained in each cryptographic service request to the cryptographic facility, control vectors need not be stored or managed outside the cryptographic facility.

Abstract: A method and system for rapid transfer of data between a system bus and an external device coupled together by a cable. A data processing system having at least one computer system, which includes an internal bus and an external device is provided wherein the internal bus is coupled to the external device via a cable. The external device includes an external processor capable of accessing data within the computer system. The data processing system also includes an interface module having a number of buffers for storing data, wherein the interface module is interposed along the cable between the computer and the external device. Control circuitry is included in the interface module for reading from and placing data into the buffers.

Abstract: A process for reducing translation look-aside buffer (TLB) purge overhead does so by purging the TLB only when required to avoid invalid entries. The translation look-aside buffer (TLB) contains virtual to real mappings for a particular address space. Operating systems commonly purge the TLB whenever a new task is dispatched to ensure the TLB entries are valid. A system with relatively short tasks will incur significant overhead by this practice. The present invention detects those situations where a purge is required by associating TLB purge with the address space allocation logic. Invalid TLB entries will exist only where an address space is re-used by a different task. The address space allocation logic is modified to place a marker indicating a TLB purge in the queue of free address space blocks. Whenever the marker rises to the head of the queue a TLB purge is issued. Task dispatches at all other times do not require TLB purging.

Abstract: A method and system for cache memory congruence class management in a data processing system. A selected address within a data processing system will typically have a single real address, but may have multiple virtual addresses within multiple virtual address spaces in a multi-tasking system, each virtual address space including a segment index, a page index and a byte index. A memory cache may be utilized to improve processor performance by hashing a portion of each virtual memory address to an address within a congruence class in the cache; however, when the cache contains a greater number of congruence classes than the number of different byte index addresses the virtual memory addresses of a single real memory address may hash to different congruence classes, reducing the ability of the processor to rapidly locate data within the cache.

Abstract: In a graphics subsystem, a highly interactive two-dimensional (2D) data stream and a computationally intensive three-dimensional (3D) data stream are processed concurrently in such a manner that processing of the 2D data stream is not held up by processing of the 3D data stream. A 3D geometry subsystem having a parallel pipeline architecture is used to process the 3D data stream, while a 2D subsystem concurrently processed the 2D data stream in parallel with the 3D subsystem. A reordering device couples the processed 2D and 3D data streams to a common raster subsystem. The reordering device, which contains an internal buffer, reorders any order-dependent elements of the 3D data stream appearing at the output of the 3D geometry subsystem in an order different from the order in which they were supplied to the input end.

Abstract: A method and apparatus for handling system service requests such as disk change requests in a system containing a primary processor and at least one secondary processor, each of which has one or more processes running thereon. Requests originating from processes running on the primary processor are added directly to a primary queue and the corresponding processes suspended pending the completion of the requested system service, at which time the processes are resumed and the requests are purged from the primary queue. Each secondary processor manages a secondary queue of system service requests originating from processes running on that processor, which are suspended while the requests remain on the secondary queue. When a request is added to an empty secondary queue, a process on the secondary processor issues its own request to the primary processor, which is added to the primary queue, and suspends execution while awaiting a response from the primary processor.

Abstract: A method of creating a data structure or map describing the I/O configuration and of verifying and resolving errors in configuration data in a system in which processors are coupled to one another or to device control units either directly or through a dynamic switch by way of links attached to link adapters of respective end units. Each pair of unit link adapters coupled to the respective ends of a link exchanges information identifying the unit and the adapter on that unit. A physical configuration map indicating the actual physical system configuration is constructed from such "nearest neighbor" information. This physical configuration map is compared with a logical configuration map indicating the user-defined logical system configuration to determine the existence of any discrepancies therebetween, and one map is conformed to the other as appropriate.

Abstract: In a computer graphics display system, a method and processor are disclosed for drawing a `polygon with edge`-type primitive encountered in certain high level graphics interface programs. Both the method and processor use a mask buffer organized into a plurality of addressable constituent pixels, each pixel preferably being two bits deep. The method includes: masking the pixels in the mask buffer corresponding to the boundary to the polygon; drawing the pixels in the frame buffer of the display system corresponding to the boundary of the polygon; and drawing the pixels in the frame buffer corresponding to the interior of the polygon with reference to the content of the mask buffer. Corresponding processing steps for writing Z values in a depth buffer are also described. In addition, specific algorithms for implementing the method are set forth, along with an embodiment of a display processor implementing the method.

Abstract: A quad oscillator fault-tolerant clock system for a computer complex comprises two clock sources at each of two computer locations, which are coupled by two duplex links. Each clock source supplies its own clock signal to the other clock source at the same location as well as to the clock sources at the other location over one of the duplex links coupling the two locations. Each clock source continually measures the phase difference between its clock signal and each of the other three clock signals. Periodically, the propagation delay for each link is calculated by taking the average of the phase differences measured by the clock sources driving the two ends of that link. These calculated propagation delays are supplied to each individual clock source, which corrects the phase differences measured by it for the propagation delays.

Abstract: A processing system for identifying operator selection of a graphics object in a system using parallel pixel generation. Parallel pixel generation results in a fragment comprising a series of M pixels being generated at each processing cycle. The image fragment must be tested against an operator defined selection area to determine whether the object being generated falls within the operator selection area. Fragments are initially classified as totally within or totally outside of the area. If a fragment intersects the operator selection area, mask is applied for each boundary of the operator defined area. Selection is signalled based upon the logical combination of the masked image fragments. Operator selection or picking occurs without the overhead of maintaining a pick RAM for the X and Y dimensions.

Abstract: A semiconductor injection laser diode is coupled via a switch to two drivers. One driver provides a drive current above the threshold current required to cause the injection laser diode to lase. The other driver provides a drive current below this threshold current, causing the laser diode to operate in a light-emitting diode (LED) mode. The switch couples the laser diode to one or the other of the drivers depending upon the receiver to which the transmitter is coupled.

Abstract: A low-cost test system for testing digital circuit elements, such as a memory array, which includes a base to provide operating voltage and an operator interface in combination with interchangeable, removable test modules. Each test module includes a test function data processor, an address generator for selecting addresses to be tested, and a comparator for comparing actual output signals with the generated expected outputs. The test function data processor has a number of stages of high-speed memory and logic to generate independently test program data, test program expected data and test address control data.