Abstract: A cached version of a file system directory is synchronized with a server version of the directory in a distributed file system. Both a server and a client specify version numbers for their directory versions. On receiving a request from the client specifying a directory update, the server updates its version, increments its version number, and transmits a reply to the client containing a change log with the incremented version number. Upon receiving the reply, the client compares the received version number with that of its cached version. If the version number matches that of the next expected update, the client applies the updates to its cached version and increments its version number. Otherwise, it adds the received change log to a change log queue for the directory without incrementing the last applied version. Mechanisms are provided for handling parallel read and update requests without awaiting replies from the server.

Abstract: A method of collecting usage data of an on-demand service provided to a subscriber is disclosed. The method comprises provisioning of a first manageable resource in order to provide the on-demand service to the subscriber, the first manageable resource being associated with at least a first underlying resource, the first underlying resource comprising a first collector for collecting first usage data of the first underlying resource while the on-demand service is provided. Further, a first metering component is instantiated for the first manageable resource and the first metering component is instructed to initiate the retrieval of the first usage data from the first collector prior to the termination of the first metering component and the de-provisioning of the first manageable resource. Additionally, the retrieved first usage data is stored for further evaluation.

Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.

Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.

Abstract: A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.

Abstract: To implement job execution in which resource assignment and change of the assignment can be dynamically and autonomously performed so as to meet requirements of a job in a job and resource environment in which the operational status cannot be forecasted in advance. A job that can be divided into a selected number of tasks is provided to one computer of a plurality of computers connected via networks, and job tasks are processed with the one computer for predetermined time. A progress rate of task processing for the predetermined time is calculated, and completion time for task processing on the one computer is estimated on the basis of the progress rate and the predetermined time. It is determined whether the estimated completion time meets requirements of the job. When the estimated completion time meets the requirements, job tasks are processed with the one computer, and results are generated.

Abstract: A method of compiling source code, involving a pre-processing step for including at least one additional source code file into the source code prior to generating target code from the source code. The proposed method further comprises the steps of: establishing, during the pre-processing step, at least one network connection to at least one remote server; and downloading the additional source code file from the remote server.

Abstract: A circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's QOR is dependent upon the prior placement's quality of result QOR, circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by stripping them from the global placement solution and also other non-degenerate poor quality placements are corrected.

Abstract: A improved method for very-early validation of voltage region physical power distribution networks uses initial floor plan and early power grid data to identify physical power connection problems associated with voltage regions defined in multi-supply voltage microprocessor chip designs. Since all checking algorithms are floor plan-based and do not require complete circuit data, they are executable very early in the design phase. As a result, power region-related problems can be resolved much sooner than by using conventional full-chip physical design checking and power grid analysis methods.

Abstract: A solution for improved monitoring and control of jobs in grid and batch computing systems provides a centralized server's batch manager which is only responsible for workload balancing and job initiation and completion, all other command and status information are communicated directly between the plurality of submitter's systems and the plurality of client systems that are processing their respective workloads. The computing system and communication process utilizes event-driven peer to peer communications between submitter's systems and client systems and enables more detailed status and control information to be passed without overloading the centralized server, and by avoiding polling also provides more immediate feedback of results. Multiple process threads are employed on both the submitter's and client systems, and a user interface consolidates and displays results to the submitter allow commands to be sent to processes running on client batch systems.

Abstract: Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle.

Abstract: Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

Abstract: A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.

Abstract: A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.

Abstract: A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.

Abstract: A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

Abstract: A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics.

Abstract: A method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.

Abstract: A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.