Abstract: A composition for optimally removing or etching metallic alloys from chemically compatible substrates with minimal damage to the substrate. The preferred composition is Ammonium Fluoride, Hydrofluoric Acid, Nitric Acid, Phosphoric Acid and Water in a specified range of quantities used to selectively remove an Aluminum and Silicon Alloy and Titanium film from a chemically compatible substrate. The composition is placed in contact with Stainless Steel, Silicon, or other organic or metallic substrates to remove, etch, or pattern homogenous or layered Aluminum, Silicon, Titanium and Copper Alloys from the substrate with minimal etching to the underlying substrate.

Abstract: Analog-to-digital (AID) converters with power line frequency noise rejection by synchronization of the converter clock with the power line frequency through a phase locked loop. Both sigma delta and integrating A/D converters may use the synchronized clock to precisely reject power line frequency noise.

Abstract: A differential comparator with inputs switched and capacitively coupled to inverters which have capacitive cross-coupling feedback for a latching operation. The inverters also have direct switched feedback for autozeroing. The inputs further have a shorting switch between the input switches and the coupling capacitors for offset compensation. Complementary operation of the switches provides precharge and evaluation phases of operation. During precharge the inputs are applied to the input coupling capacitors and the inverters are autozeroed; during evaluation the inputs are transferred to the inverters through the coupling capacitors and the outputs feedback positively through the cross-coupling capacitors to latch the pair of inverters.

Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.

Abstract: An ALU comprising a tree-based carry structure, wherein the maximum fanout from any gate in the carry structure is three. When calculating optimized fanout, it is necessary to consider input capacitance to the following stage. In minimizing propagation delay, it is necessary to consider loading and the number of stages. It has been recognized that optimum fanout of results in optimized propagation through the ALU, thus fanout of three is the closest whole number. A cell has been designed which includes the necessary and sufficient circuitry for building multicell ALU's in a highly optimized structure. The cell provides individually accessible components and dedicated components for optimum layout in the end product.

Abstract: A distributed amplifier having an on chip DC biasing network including a spiral inductor. The spiral inductor has a low resistance for providing a minimal resistance path for the DC biasing, while also having a high inductance for isolating the RF signal from the DC bias sources. Additionally, an inductive lead connected between the spiral inductor and the amplifier has a predetermined inductance such that this inductance is matched with the inherent capacitance of the spiral inductor in order to provide a substantially same impedance as that of the amplifying stages.

Abstract: A method of manufacturing semiconductors formed of bonded wafers. The method includes the use of a heat sink. The heat sink induces a temperature gradient to occur on a single area at the interface of the wafers with the gradient moving rapidly across the remaining surface. As a result of the temperature front, the voids or uncontacted areas between the wafers which result in a typical bonding process are substantially reduced, thereby providing a stronger and more effective bond.

Abstract: A method of forming a high quality dielectrically isolated silicon on insulator semiconductor device using a double wafer bonding process. As a result of the double wafer bonding process, the invention significantly reduces the device limitations presently known with dielectric isolation and silicon on insulator structures. The present invention specifically eliminates the need for grinding or polishing the final surface which the devices will be implemented in, thereby eliminating the adverse effects which these mechanical processes impute onto these surfaces. Additionally, the present invention eliminates the need for a thick polycrystalline deposition for the production of the dielectric isolation, thereby eliminating the adverse effects of single crystal bulk defects and the loss of tolerance control due to warpage which would otherwise occur in a dielectric isolated process.

Abstract: A process for the formation of a compact vertical contact having reduced lateral space requirements yet compatible with highly planarized semiconductor manufacturing processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer can be contacted on its edge rather than on its top surface in order to reduce the lateral expanse of the contact.

Abstract: A monolithic semiconductor having an on-chip DC biasing including a plurality of series connected spiral inductors connected between the respective biasing and the semiconductor circuit. The spiral inductors provide a low resistive path for the DC biasing while also having a high inductance for isolating the RF signal from the bias sources, thereby improving the low frequency response. The capacitance associated with the individual spirals, however, is significantly less than the capacitance associated with a single spiral inductor having an equivalent inductance of the small series connected spirals; thus the higher frequency response is not degraded while the low frequency response has been improved.

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.

Abstract: A pallet for conveying a plurality of ceramic leadless chip carriers (LCC) through an automated wave soldering machine. The pallet includes recesses formed to receive and contain the LDD's with the lid of the LCC facing into the recess. This results in protecting the lids from the molten solder. Additionally, the recesses are formed in a diamond orientation with a solderable pin placed at the trailing apex of each recess. Both the pin and the diamond orientation prevents solder build up on the trailing conductive pads, resulting in enhancing the coplanarity of the solder on the pads.

Abstract: A process for manufacturing an insulated gate field effect semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the gate region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the gate. Contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the gate from the contacts.

Abstract: The front end of an operational amplifier having an improved slew rate and high gain current output capabilities. The amplifier includes a slew enhancement or large signal stage connected in parallel to a normal front end or small signal stage. The small signal stage supplies a transconductance output which is approximately linearly related to the input until its slew rate limit. The slew enhancement stage is designed to provide slew current when the small signal stage reaches a selected threshold such as its slew rate limit, thereby providing an increased output current response to an increasing differential input voltage beyond the slew rate of the small signal stage. The large signal stage can be optimized to provide a greater input linear dynamic range, faster slew rate and improved efficiency.

Abstract: A method of forming a high quality silicon on insulator semiconductor device using wafer bonding. The annealing time for the wafer bonding process is substantially reduced through the use of a rapid thermal annealer, thereby resulting in minimizing the redistribution of the doping concentration resulting from the annealing process.

Abstract: A programmable logic circuit which can be implemented on a single integrated circuit in conjunction with other associated circuitry. The circuit includes programmable fuses whereby the circuit can be programmed to implent AND, NAND, OR, or NOR functions. Additionally, the circuit can be programmed to accept either a high or low true logic on each individual input as well as providing either a high true or low true output.

Abstract: A high efficiency integrated power converter adapted for direct connection to line voltage and having on chip protection from overcurrent may be implemented utilizing a GTO-SCR as the switch element in a switching power converter such that the converter requires no external transformer or inductor based voltage reducing circuitry. The input voltage may vary over a wide dynamic range without deterioration in circuit performance due to the extremely high anode to cathode breakdown voltage of the switching element and further due to the on chip protection from excess current flow through the switching element.

Abstract: A process for manufacturing a bipolar semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the emitter region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the emitter. Conductive contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the base from the contacts.