Abstract: A system and method is provided for providing a deadband switching time delay. One embodiment of the present invention includes a switching regulator system. The switching regulator system includes a control circuit configured to alternately activate a high-side power switch and a low-side power switch of the switching regulator system. The switching regulator system also includes a switching delay element configured to provide a switching deadband associated with a logic state transition delay of at least one of the high-side power switch and the low-side power switch, the delay element comprising a programmable coarse delay element to provide a course delay amount and a programmable fine delay element to provide a fine delay amount.

Abstract: Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect.