Abstract: One embodiment of the invention includes a power driver system. The power driver system comprises a power transistor that is activated to provide power to a load and a switching circuit configured to control the power transistor based on a control signal. The power driver system further comprises a control circuit configured to detect a flyback current from the load upon deactivation of the power transistor and to cause the switching circuit to steer the flyback current from a first flyback current path to a second flyback current path in response to detecting the flyback current path. The second flyback current path can have an impedance that is greater than the first flyback current path.

Abstract: A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage limiter circuit. The voltage limiter generates a limited voltage. A voltage regulator is coupled to the limited voltage for generating a regulated output voltage. The voltage regulator has a dynamic biasing current responsive to an output of the sensing element for increasing bandwidth of the voltage regulator when current in the voltage limiter circuit increases.

Abstract: According to one embodiment of the invention, a network system for carrying control data between a controller and a device to be controlled is provided. The network system comprises a bus system operable to carry data between the controller and the device according to an IEEE 1394 standard. The IEEE 1394 standard defines a start up operation that includes one or more sequences. The bus system is also operable to perform a modified start up operation that excludes at least one of the sequences of the start up operation defined by the IEEE 1394 standard.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.

Abstract: A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element.

Abstract: There is provided a power supply monitor circuit comprising a positive supply monitoring input, a negative supply monitoring input, and a voltage divider connected between the positive and negative supply monitoring inputs and having an intermediate node providing a potential intermediate those on the positive and negative supply monitoring inputs. A sampling circuit is connected to sample the potential at each of the positive supply input the negative supply input and the intermediate node. Also provided is a method of monitoring noise on a power supply whereby phase information from those samples is derived about the noise signals at the two said points.

Abstract: A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor structure (DR1) and a second MOS transistor structure (DR2) have their channels connected in series such that they function as a second rectifying diode, the cathode of the first rectifying diode being connected to the anode of the second rectifying diode. The first MOS transistor structure (DR1) and the second MOS transistor structure (DR2) are spaced from each other such that a distance between the two MOS transistor structures is large enough that a parasitic npn-structure formed within the substrate by the first and the second MOS structures has a negligible current gain.

Abstract: A system that has a pseudorandom number generator and a mapping system. The pseudorandom number generator generates a random number that is mapped by the mapping system to an output value that is selected from a set of predetermined output values. To increase the randomness of the sequence of numbers generated by the pseudorandom number generator, a tap and/or seed value of the pseudorandom number generator can be varied.

Abstract: A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time slot for the transmission of one data packet from a selected one of the plurality of data queues. There is one arbitration logic circuit for each of the plurality of entries in the arbitration table. Each arbitration logic circuit includes a first multiplexer receiving an output from a first table entry and an output from a second table entry in the arbitration table. A second multiplexer receives empty flags from each of the data queues, the flags indicating that there is no data to the sent from that queue.

Abstract: A CAN communication module (10) comprising a protocol kernel (14) and a CAN logic block (12) is provided. The protocol kernel includes a CAN bus interface and the CAN logic block includes a module interface for connection to an external peripheral bus (22), a message RAM (28) and a CAN message handler (26). The protocol kernel (14) and the CAN logic block (12) have separate clock inputs (32,36).

Abstract: The invention provides an improved dynamic element matching (DEM) device. The DEM device performs dynamic element matching processing at a second timing rate different from the first timing rate for the digital input. As an embodiment, the DEM device is composed of encoder 10 and feedback circuit 12. Said encoder 10 has two inputs and one output. Of the two inputs, one receives the digital input as the object for the DEM processing, and the other input receives the output of feedback circuit 12. Then, the digital output of the encoded result is generated. Said feedback circuit 12 has sampling rate converter 120 and loop filter 122 in order to perform DEM processing at a timing rate different from the timing rate for the digital input as the DEM processing object.

Abstract: Methods and apparatus to test power transistors of integrated circuits on a wafer are disclosed. An example method comprises measuring a drain-source on resistance of a first transistor, measuring a drain-source on resistance of a second transistor, computing a scaling ratio between the transistors based on the drain-source on resistances of the transistors, measuring a first current indicative of an over-current condition of the first transistor, and computing a second current of the second transistor based on the current of the second transistor and the scaling ratio.

Abstract: The bias current of a current injection-type light-emitting element is set very close to the threshold current, and to guarantee a stable optical output and high-speed initiation of the light-emitting operation. In the bias current supply circuit 12, particularly in closed-loop circuit 20, feedback operation of bias APC with variable bias current Ib is performed so that monitor voltage VM1 comes to equal reference voltage VA1. With this feedback operation, the steady state of VM1=VA1 is reached, and drive current Ib (Iba+Ibb) sent to laser diode 10 converges to a constant value. After a prescribed time, S/H circuit 34 is switched to hold mode. As a result, drive current Ib (Iba+Ibb) is temporarily held to a constant value corresponding to the prescribed optical output.

Abstract: The objective of this invention is to provide a drive circuit and display system that can efficiently transfer prescribed information indicating an abnormality in the drive current supplied to the display elements to a control device. The control data used for controlling the turning on and off of LEDs are shifted sequentially from the first section to the final section of LED drivers 10-1-10-K connected in cascade. In the drive circuit of each section, the control data input from the previous section are held in the first data holding means synchronously with clock signal CLK. Then, the data held in the first data holding means are held in the second data holding means synchronously with latch signal XLAT. Current corresponding to the control data of the second data holding means is supplied to LEDs 40-1-40-M. On the other hand, when new control data are held in the second data holding means, the data indicating prescribed information concerning abnormal functioning of the LED, etc.

Abstract: A system and method is provided for driving a power field-effect transistor (FET). In one embodiment, a system comprises a control circuit that generates a control signal to provide a gate voltage of the power FET. The system further comprises a slope control circuit coupled between the control circuit and the power FET that is operative to dynamically control the rate-of-change of a gate voltage of the power FET to reduce electromagnetic interference (EMI) emissions and power loss resulting from switching the power FET.

Abstract: A solid-state image pickup device that can suppress the dark current with respect to the photo-electrons overflowing from the photodiode, as well as its manufacturing method. Each pixel has the following parts: photodiode, transfer transistor, floating diffusion, accumulating capacitive element, and accumulating transistor.

Abstract: A method that does not rely on signal strength for detecting the presence of a broken optical wireless link. The method controls the packet transfer rate in a manner that minimizes both network overhead and computational requirements. Upon completion of the acquisition process, the control packet transfer rate is significantly reduced, since a high control packet transmission rate is only necessary during the acquisition process in order to expedite the acquisition process. The need for reacquisition is based, for example, on the number of consecutive missing packets, or the rate of missing versus received packets.

Abstract: A method for gradually increasing the brightness of an indicator light. An activation signal is received indicating that the indicator light should be lit. Upon receipt of the activation signal, the brightness of the indicator light gradually increases. Upon detection of deactivation of the activation signal, the indicator light is extinguished.

Abstract: In a method and system for testing a transceiver communication device operating in a test mode, a transmitter output signal generated by a transmitter is adjusted and provided as a loop back to a receiver. The adjustment includes shifting a frequency and attenuating amplitude of the transmitter output signal to substantially match a predefined frequency and a predefined amplitude of a receiver input signal received by the receiver. A pass or fail status of the device is determined by comparing transmitted and received data.

Abstract: An integrated phase adjusting circuit (12) for the generation of a clock output signal (CLKout) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is proposed. The circuit has an interpolator unit (30) which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, and is controlled externally by a control signal (PHfine) to execute a phase step if the phase of the clock signal is to be shifted. The circuit (12) comprises a synchronization unit (40) which synchronizes the phase step with the clock output signal generated by the circuit.