Abstract: A method for simultaneous fabrication of an interlever metal contact and a fuse window reducing the number of masking steps required while providing a high yield for the fuse. A semiconductor substrate is provided having a device area with a first metal layer over an InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within the InterLevel Dielectric layer. A thick anti-reflective coating is formed on the first metal layer. The first metal layer and the anti-reflective coating are patterned to form a first metal line. An InterMetal Dielectric layer is formed over the InterLevel Dielectric layer and the first metal line. The InterMetal Dielectric layer, the InterLevel Dielectric layer, and the anti-reflective coating are patterned, simultaneously opening a via hole extending partially into the anti-reflective coating and a fuse window opening extending into the InterLevel Dielectric layer without exposing the fuse. An adhesion layer is formed over the InterMetal Dielectric layer.
Type:
Grant
Filed:
February 11, 1999
Date of Patent:
December 28, 1999
Assignee:
Vanguard International Semiconductor Corporation