Abstract: Two independent power supplies for an I.sup.2 L or ISL logic array can be timed to turn on at different times by a simple RC network connected externally of the logic array. The differential timing is utilized to condition or set a bistable device in a predetermined initial desired state, without requiring an additional device terminal pin for that purpose.
Abstract: A single flip flop is integrated with MOS circuitry which enables the single flip flop to be triggered by each of several individual clocked functions without interfering with one another. The flip flop responds only to low to high transitions of each clock signal input. This is accomplished by feeding back the flip flop output to each trigger circuit in such a way as to temporarily disconnect the trigger circuit from the flip flop during the time period between two successive low to high transitions of a particular clock signal, so that the flip flop can be triggered by other clocked functions without interference from the particular clock signal.
Abstract: A high density semiconductor structure and method is disclosed including a semiconductor body of one conductivity having a substantially planar surface. A first region of one conductivity is formed in the body and extends to the surface. A layer of opposite conductivity is interposed between the first region and the body said layer having relatively thin and uniform walls which extend to separate the first region from the body. At least one opposite conductivity region is formed entirely within the first region and extends to the surface. An opposite conductivity region is formed in the body and overlaps a portion of the layer. Lead means are provided for contacting each of the respctive regions and the body. The collector-up injection logic structure thus formed requires little or no surface area for the injection source transistor.
Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different weighted levels of injection current. The switching states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistor are connected and to the weight of the injection current associated with the output transistor.
Abstract: Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal.
Abstract: Solid state folded leaf spring force transducers are fabricated by batch photolithographic and etching techniques from a monocrystalline material, such as silicon. The folded leaf spring structure includes elongated gaps separating adjacent leaf spring leg portions, such elongated gaps being oriented parallel to a crystallographic axis of the monocrystalline material. In a preferred embodiment the monocrystalline material is of diamond cubic type and the leaf spring gaps extend in mutually orthogonal directions parallel to the <011> and <011> crystallographic axes, respectively. In a preferred method of fabricating the spring structure, the structure is etched from a monocrystalline wafer by means of an anisotropic etchant so as to more precisely define angles and dimensions of the resultant spring structure.
Abstract: An amplifier circuit and structure having high input impedance and having a return path for conducting amplifier DC leakage current. A common diode structure forms the return path and includes two diodes connected in series and connected in opposite conduction directions. The diode having a forward conduction direction which is in the opposite direction of the leakage current is provided with a reverse saturation current which is substantially greater than the leakage current of the amplifier. The amplifier is typically a P channel or N channel field effect transistor (FET) and the double diode structure is typically an NPN or PNP transistor.
Abstract: A universal differential line driver with a single pair of outputs provides by means of a pair of control input lines selectively sourcing, sinking or high impedance conditions on the output pair.
Abstract: Semiconductor assembly and method in which very small pill-like packages can be mounted directly on boards and can be directly mounted in assemblies and stacks. The pill-like package encapsulates a semiconductor body having at least a portion of an electrical circuit formed therein with contact pads in a predetermined pattern carried by the body and lying in a common plane with a plurality of first leads bonded to the contact pads and the first leads extending outwardly from the semiconductor body and having outer extremities which lie in a predetermined pattern with encapsulating means encapsulating the semiconductor body and the portions of the first leads in engagement with the contact pads. The pill-like package is very small and has a spider-like conformation. The leads are formed in such a manner so that the packages can be directly mounted upon printed circuit boards without extending the leads through holes. The pill-like packages can be stacked into assemblies in which the leads are interconnected.
Abstract: Defect formations and unwanted in diffusions caused by residual impurity products is prevented in a semiconductor fabrication method which includes the step of forming a composite mask which simultaneously defines base, collector and diffusion isolation openings. After these openings are defined a thin protective layer of silicon dioxide is grown over the exposed area and remains there throughout the remainder of the doping process which includes the steps of selectively covering areas which are not to be doped with photoresist and thereafter ashering the photoresist to remove it in preparation for the next ion implantation step. The thin protective layer of silicon dioxide protects nonselected areas against residual impurity products formed during removal of the photoresist.
Abstract: A logic circuit for converting a triple state input to a binary output having a single line ternary input and a two line binary output. A pair of output transistors provide the two line binary output, and means are provided for driving both of these output transistors, such that three different binary output states result from the ternary input states of low, high and open (or floating), respectively.
Abstract: In a semiconductor structure, a semiconductor body of one conductivity type having a planar surface and a first region of opposite conductivity formed in said body and extending to said surface. Spaced second, third and fourth regions of one conductivity type are formed in said first region and extend to said surface. Fifth and sixth regions of opposite conductivity are respectively formed entirely within said second and third regions and extend to said surface. In addition a seventh region of one conductivity type may be formed spaced from said second, third and fourth regions and an eighth region of opposite conductivity type formed entirely within said seventh region. A method for forming the semiconductor logic structure is also disclosed.
Abstract: Single bipolar transistor memory cell in which information is stored on the collector to substrate capacitance. This capacitance may be enhanced by an additional diffused region. Storage and retrieval of information is accomplished through only two leads connected to the transistor which is operated so that a portion of the base is fully depleted during a portion of the operating memory cycle of the memory cell.
Abstract: A MOS semiconductor device and method for forming same, including a semiconductor body of first conductivity type having a planar surface, said body having spaced grooves therein opening through said surface with insulating material filling said grooves and extending to the surface of said body. Spaced source and drain regions of second conductivity type are formed in the body in areas between said grooves filled with insulating material extending to the surface, and providing a channel region therebetween. An insulating layer is formed on said surface, and having a portion of relatively precise thickness overlying the channel region. A layer of semiconductor material is formed on said portion of the insulating layer, a protective layer formed on said insulating layer and said layer of semiconductor material, and lead means formed on said protective layer and extending through said protective layer to contact said source and drain regions and said semiconductor layer.
Abstract: A decode driver useful in decoders for memory circuits. A plurality of transistors are connected in series between a first reference potential terminal and an output terminal. A second plurality of transistors are connected in parallel between a second reference potential terminal and the output terminal. Each of the transistors receives an input which functions to turn the transistors either on or off. The coding of the inputs determines whether the transistors to which the respective inputs are connected are turned on or off which in turn controls whether or not the output terminal is coupled to the first reference potential terminal or the second reference potential terminal.
Abstract: A 4 .times. 4 multiplier uses four bit threshold logic type adders. The multiplier per se is arranged in a carry save configuration with first level pseudo type carry-look ahead with the highest weight bit of the product being accomplished by a wired OR connection. The four bit adder itself provides two double threshold detectors responsive to logic levels provided by a level shifter which shifts the logical voltage levels produced by a differential amplifier which sums the four inputs of the adder circuit. This provides the sum output; an additional double threshold detector provides the first carry output and a typical threshold AND gate the second carry output.
Abstract: A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.