Abstract: An audio processing system applies a filter to convert the audio signals generated by the microphone of a combined microphone/speaker earpiece into filtered audio signals, where the filter is designed to correct for distortions in the audio signals that result from the microphone being part of the combined earpiece.

Abstract: A power supply apparatus includes a front panel, a rear panel and two left and right side panels which together form a housing. Opposed edges of a partition are connected to the front and rear panels to thereby divide the interior space of the housing into upper and lower chambers. The left and right side panels each have edges which are placed to abut against the corresponding edges of the other side panel.Components of a power supply circuit are appropriately distributed in the upper and lower chambers. Some of the components in the upper chambers are located beneath the upper abutting edges of said left and right side panels, and a cover is disposed to cover at least those components which are located beneath the upper abutting edges.

Abstract: DC power from a smoothing capacitor is converted into high frequency power by an inverter, and then lowered by an output transformer. The lowered high frequency power is converted into DC power by an output rectifier and a DC reactor, and then supplied to a load. The load is short-circuited and then opened to initiate arcing. The short-circuiting and the arcing alternate. An auxiliary rectifier provides a load-voltage representative signal, and a current detector detects a load current. A load-current representative signal is differentiated by a differentiation circuit. The signals from the auxiliary rectifier, the current detector and the differentiation circuit, and a reference signal are applied to an operational amplifier. A control circuit controls the inverter such that the output of the operational amplifier can be zero.

Abstract: A plurality of parity bits is generated for serial transmission of a word of data bits, and the plurality of parity bits is modified before transmission to encode a sideband signal. The word of data bits and the plurality of modified parity bits are serially transmitted. In another embodiment, a serially-transmitted code word comprising a word of data bits and a plurality of parity bits is received, wherein the parity bits have been generated by an encoder and transmitted with the data bits. It is determined whether the parity bits were modified by the encoder to encode a sideband signal, and at least one of error detection and error correction is performed using the parity bits.

Abstract: In block based video compression, a frame is divided into blocks which define a tiling pattern. The tiling pattern is varied from frame-to-frame to prevent an accumulation of errors which tend to appear at tile edges and can increase over time when using block-based compression. In a preferred embodiment, a normal frame is padded by a border all around the normal frame size. The padding is operable to extend any blocks around the periphery of the image frame which might be smaller in dimension than the standard blocks, such as those within the interior of the frame, such that they can be treated by the block-based compression systems as full size blocks.

Abstract: Transmitting data chunks in a computer system having different computing ring levels. A data chunk is accepted by a relatively low priority ring module from a relatively high priority ring source. The address of the data chunk is translated into the address space of the low priority ring module. The low priority ring module is notified of the availability of the data chunk.

Abstract: An inverter includes a series circuit of two current conducting units connected between two input terminals adapted to be connected to a DC power supply. Two first capacitors are connected in series between the two input terminals. A primary winding of a transformer is connected between the junction of the current conducting units and the junction of the first capacitors. Each of the current conducting units includes a parallel circuit of an IGBT, a diode and a second capacitor. The IGBT has a collector, an emitter and a gate and is rendered conductive when a control signal is applied to the gate while a voltage of a predetermined polarity is applied between the collector and the emitter. The diode is connected in inverse parallel with the IGBT. An inverter control circuit applies alternately the control signals to the respective IGBTs with a predetermined quiescent period disposed between the respective control signals applied.

Abstract: For each image, an initial set of quantization (Q) levels is selected based on the pixel data. The pixel data are transformed to blocks of transform coefficients. The initial set of Q levels is incremented and decremented. The incremented Q levels are used to generate a low estimate of bitrate for the transform coefficients and the decremented Q levels are used to generate a high estimate of bitrate for the transform coefficients. The low and high bitrate estimates are compared to a specified target bitrate to generate Q-level adjustments. The Q-level adjustments are used to select the Q levels to encode fully the quantized coefficients of the current image in the sequence of images.

Abstract: For the fixated cryopreservation of single living biological objects or s objects compiled in a given number (for example cells) a cryogenically cooled substrate (13) is jetted therewith in a enveloping solution in microdroplet form (12) from a storage vessel, for example by means of a microdroplet jetting device (11). The substrate is temperature-controlled via a coolant (15), the surface to be jetted being located in a gas atmosphere or in vacuum (14). The substrate surface is maintained at a temperature T1 resulting in freezing of the impinging microdroplet, the substrate surface being possibly supportingly microstructured and comprising sensing elements. By controlled movement of either the substrate or the microdroplet jetting device the microdroplets can be applied singly and in patterns in arrays freely selectable or predetermined by the structuring of the substrate.

Abstract: Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing--an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources--a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.

Abstract: A DC power supply apparatus includes an input-side rectifier which rectifies an input AC voltage and supplies the rectified voltage to a voltage-boosting converter. The voltage-boosting converter converts the supplied voltage to a voltage of a predetermined magnitude. The predetermined magnitude voltage is, then, converted to a high-frequency voltage by an inverter and applied to a primary winding of a transformer. An output-side rectifier rectifies a high-frequency voltage induced in a secondary winding of the transformer. The inverter includes IGBTs and diodes, which are connected in a full-bridge configuration. A capacitor is connected in parallel with each IGBT. When the IGBTs are rendered conductive by the charging and discharging of the capacitors, no current flows through the IGBTs, and when the IGBTs are rendered nonconductive, the voltages applied to the IGBTs are made to become zero.

Abstract: A presentation is divided into different components. For example, a multimedia presentation may have an audio component and a video component. Each component is assigned a different network address for transmission of the presentation over the network by a server. Each receiver selects those components it wishes to play by selecting the appropriate network addresses. The presentation data is routed through the network based on the selections made by the various receivers. If, for example, one or more receivers are part of a local area network (LAN) separated from the server by a wide area network (WAN) link, and if none of those remote receivers has selected one or more of the presentation components, then the routers will not transmit data for those unselected components to the remote LAN. As a result, WAN link transmission bandwidth is preserved for desired data. In addition, the remote receivers do not have to expend processor time to examine and discard unwanted data.

Abstract: The resolution of one or more components of image data is changed to generate scaled image data and transparency processing is applied to the scaled image data, wherein the transparency processing is taken into account during the changing of the resolution of the image data. In a preferred embodiment in which a video codec applies transparency processing during the compression of subsampled video data, the capture processor applies the same transparency mask during data subsampling to decrease color-bleeding effects that may otherwise appear in the decoded video stream.

Abstract: DC power supply apparatus includes an input-side rectifier for converting an AC signal from an AC power supply into a DC signal. A DC-to-high-frequency converter converts the DC signal into a high frequency signal in response to a control signal from a control unit. An output-side rectifier converts the high frequency signal into a DC signal and applies it to a load. An input current detector detects an input current flowing through the input-side rectifier and generates a signal representative of the input current. A load current detector detects a load current flowing through the load and generates a signal representative of the load current.

Abstract: Blocks of video images are characterized as being part of either scene foreground or background for encoding. The foreground/background segmentation analysis involves a pixel level and a block level. During the pixel level, interframe differences corresponding to each original image are thresholded to generate an initial pixel-level mask. A first morphological filter is applied to the initial pixel-level mask to generate a filtered pixel-level mask. During the block level, the filtered pixel-level mask is thresholded to generate an initial block-level mask. A second morphological filter is preferably applied to the initial block-level mask to generate a filtered block-level mask. Each element of the filtered block-level mask indicates whether the corresponding block of the original image is part of the foreground or background. In a preferred embodiment, both morphological filters filter out isolated mask elements.

Abstract: Visual data in a first color format stored in first memory locations are merged with visual data in a second color format, which different from the first color format, stored in second memory locations to form a merged pixel stream. An analog signal is generated representative of the merged pixel stream. In a preferred embodiment, one set of visual data is graphics data in an 8-bit CLUT format and the other set is video data in an 8-bit packed YUV9 format (also known as the 4:1:1 format). In this embodiment, the video data is unpacked and chromakeying is applied to generate the merged pixel stream.

Abstract: A request is received from a caller to perform a read of data from a storage area of a computer system, the data having master header data in a header portion. The master header data is replaced with alternate header data before returning the data to the caller. The data, including the alternate header data, is returned to the caller. A request is received from the caller to perform a write of caller data to the storage area, the caller data having caller header data in a header portion of the caller data. The write of caller data is allowed only if the caller header data is identical to the master header data.

Abstract: The audio manager provides an interface between one or more upper-level conferencing drivers of the conferencing system and one or more lower-level audio drivers of the conferencing system to isolate the conferencing drivers from the audio drivers. The audio manager is adapted to perform a plurality of functions called by the conferencing drivers. The audio manager comprises a local audio stream state machine and a remote audio stream state machine.