Abstract: A digital video encoder is presented adapted for dynamically switching between sets of quantizer matrix tables without pausing encoding of a stream of video data. Two or more sets of quantizer matrix tables are held at the encoder's quantization unit and compressed store interface for dynamically switching between sets of quant matrix tables at a picture boundary of the sequence of video data, i.e., without stopping encoding of the sequence of video data. Further, while one set of matrix tables is being employed to quantize the stream of video data, the encoder can be updating or modifying another set of quantization matrix tables, again without stopping encoding of the sequence of video data.

Abstract: A transport demultiplexor system and queue remultiplexing methodology includes: a packet buffer for receiving data packets belonging to an input transport stream, each packet having a corresponding identifier identifying a program to which the packet belongs; a data unloader device for pulling successive packets from the packet buffer for storage in a memory storage device, and writing the pulled packets into contiguous address locations in the memory; and, a remultiplexor mechanism for generating an address offset associated with a next data packet pulled from the packet buffer to be stored in memory and writing it to a new memory location that is offset from a memory location assigned to a previously pulled packet, the offset defining a memory gap in the memory storage device capable of being filled new data content.

Abstract: A technique is provided for encoding macroblocks of a frame of a sequence of video frames initially employing luminance data only to analyze temporal redundancy of the macroblocks within the frame. Upon deciding to code at least one macroblock as a non-intra macroblock, the technique includes considering whether to switch the coding decision for the at least one macroblock from non-intra to intra by evaluating chrominance data of the at least one macroblock. The evaluating of the chrominance data can include determining whether chrominance difference data, obtained by comparing chrominance values of a current macroblock with a reference macroblock, is greater than a user set chrominance difference threshold, and if so then the technique includes switching the macroblock coding decision. As a further qualification, the switching might occur only if the chrominance difference data is also greater than the corresponding luminance difference data.

Abstract: An apparatus used for video encoding MPEG compliant digital visual images, having multiple MPEG encoders used in the motion estimation function. The search capabilities used in the motion estimation function of a single MPEG encoder are extended beyond its design limitations as a result of utilizing more than one MPEG encoder. The utilization of multiple encoders effectively creates the capability for a user to specify a wider search window than what is available in a single encoder configuration. The computational search efficency associated with searching the wider window is not adversely affected as a consequence of the multiple processors subdividing the extended window and analyzing each subdivision in parallel.

Abstract: A technique is provided for aligning and formatting multi-operand pixel data, for example, within a pixel formatter of a graphics engine for a set-top box system. The technique includes, in one embodiment, obtaining pixel data of a first alignment and a first format for conversion to a second alignment and a second format. The pixel data undergoes pre-alignment where the first alignment of the pixel data is changed to a bit zero alignment, after which the pixel data is reformatted from the first format to the second format. The reformatted pixel data is post-aligned to change from bit zero alignment to the second alignment. In one embodiment, the pixel data is source pixel data or pattern pixel data, while the second alignment and the second format are alignment and format of destination pixel data.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. HDTV signals are decoded using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Abstract: A method for reducing the number of wire-bond loop heights which are required in comparison with a total quantity of power and signal rings employed in low profile wire-bond integrated circuit packages. There are also provided low profile wire-bond packages which are produced in accordance with the method pursuant to the invention.

Abstract: A technique is provided for programmably controlling output of compressed data from, for example, a video encoder. The technique can be implemented within the video encoder and includes buffering the compressed data in a write buffer, followed by transferring the compressed data from the write buffer to a read buffer. At least one programmable output mode is provided for selectively controlling output of the compressed data from the read buffer. When the read buffer is full, the compressed data is stored to the encoder's external memory to await transfer to the read buffer. The at least one programmable mode can include a slave mode, a gated master mode, a multi-cycle speed mode, and a paced master mode, which may be employed individually or in combination. A mechanism for inserting pad bytes of data into the compressed data is also provided.

Abstract: A processing facility is provided for simultaneously receiving multiple streams of digital audio data and based thereon concurrently outputting both an unmixed digital audio signal and a mixed digital audio signal. The processing facility can be implemented, for example, within an audio decoder of a set top box. The facility includes receiving a first stream of digital audio data and a second stream of digital audio data, and outputting the first stream of digital audio data as an unmixed digital audio signal. Simultaneous therewith, the first stream of digital audio data and the second stream of digital audio data are digitally mixed and outputted as a mixed digital audio signal. If necessary, the second stream of digital audio data is redigitized based on a sample frequency of the first stream of digital audio data, and either or both the first stream and second stream of digital audio data are decoded prior to mixing.

Abstract: Techniques are provided for initializing, maintaining, updating and recovering secure operation within an integrated system. The techniques, which employ a data access control function within the integrated system, include authenticating by a current level of software a next level of software within an integrated system. The authenticating occurs before control is passed to the next level of software. Further, an ability of the next level of software to modify an operational characteristic of the integrated system can be selectively limited via the data access control function. Techniques are also provided for initializing secure operation of the integrated system, for migrating data encrypted using a first key set to data encrypted using a second key set, for updating software and keys within the integrated system, and for recovering integrated system functionality following a trigger event.

Abstract: Apparatus, method and computer program product are provided for performing integrity checking of a relocated executable module loaded within memory by an operating system loader. A repeatable digital signature is generated by determining the load address of the executable module in memory, normalizing at least some content of the executable module in memory employing the load address of the module, and then performing integrity analysis on a digital section of the module's content, including the normalized content, thereby deriving the repeatable digital signature.

Abstract: A technique for transferring data between a first device and a second device using a shared line buffer connected to a system bus which couples the first device and the second device. The technique includes (i) transferring data between the line buffer and dedicated memory associated with the first device, wherein the first device includes a data controller coupled to the system bus through a bus interface. The transferring (i) includes using the data transfer controller to effectuate a multiword data transfer between the dedicated memory and the line buffer. The technique further includes multiword data (ii) transferring between the line buffer and the second device across the system bus. When the transferring (i) precedes the transferring (ii), data is read from the dedicated memory from output to the second device, and when the transferring (ii) precedes the transferring (i), data is written to dedicated memory from the second device.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: An output driver impedance calibration circuit which is used to make I/O (input/output) off chip driver characteristics, for a plurality of output driver circuits, alike on the same chip. The output impedance of an input/output driver circuit is calibrated by providing an external target impedance reference (it could be a multiple of the actual target output impedance), multiple devices in the output stage of the I/O driver circuit, a circuit to determine the value of the actual output impedance as compared with its target output impedance and a determination of when to stop the calibration process.

Abstract: A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: A substrate that is substantially non-wettable to adhesive resin is disclosed. The substrate is coated with a fluorinated silane composition. Preferable fluorosilane compositions include perfluoroalkyl alkylsilanes of Formula III: R5nR6mSiX4−(n+m)  III wherein R5 is a perfluoroalkyl alkyl radical; R6 is alkyl or alkenyl; X is acetoxy, halogen or alkoxy; n is 1 or 2; and m is 0 or 1. The composition is preferably applied in solution and upon evaporation of the solvent, forms a durable, non-wetting, yet well-adhering surface. In a preferred embodiment, the substrate is a chip carrier with enhanced wire bondability for use in the manufacture of a semiconductor device.

Abstract: An on-screen display processor for a digital video signal processing system is disclosed. The OSD processor includes logic for converting a graphics bitmap in 4:4:4 format to graphics image words in 4:2:2 format for blending with video image words in a blend multiplexer of the digital video decode system. The OSD processor provides the graphics image words with blended chrominance values each obtained by merging chrominance values of at least two adjacent picture elements of the graphics bitmap. The merging includes mathematically combining U chrominance values of the at least two adjacent picture elements to produce a blended U chrominance and mathematically combining the V chrominance values of the at least two picture elements to obtain a blended V chrominance. In one embodiment, the mathematically combining comprises averaging the U chrominance values to obtain the blended U chrominance and averaging the V chrominance values to obtain the blended V chrominance.