Abstract: A self-aligned silicide process that enables different silicide thicknesses for polysilicon gates and source/drain junction regions. Semiconductor body (10) includes a doped well (14) formed in substrate (12). Field insulating region (18) is located above channel stop region (16) in doped well (14). Implanted within doped well (14) are source/drain junctions (34). Source/drain junctions (34) are shallow heavily doped regions. The surfaces of source/drain junctions (34) are silicided. Silicide gate (44) is separated from the surface of doped well (14) by gate insulator layer (20) and contains a silicide layer (40) and a doped polysilicon layer (22). The thickness of silicide layer (40) is not limited by the thickness of the silicided surfaces of source/drain junctions (34) or the amount of silicon consumed over these junctions. Silicon nitride sidewall spacers (32) separate the sidewall edges of silicide gate (44) and the transistor channel region from the source/drain junction silicide layer 41.

Abstract: One embodiment of the present invention is a gated thyristor formed at a face of semiconductor layer of a first conductivity type, comprising: a first well formed at the face to be of a second conductivity type opposite the first conductivity type; a second well of a first conductivity type formed at the face to be enclosed by the first well; an emitter region of the second conductivity type formed at the face to be enclosed by the second well; first and second highly doped regions formed at the face to be of the first conductivity type, the first highly doped region formed within the first well and the second highly doped region formed in the first well and at least partially within the second well, a subregion of the first well spacing apart the first and second highly doped regions and operable to act as a base of a first bipolar transistor; third, fourth and fifth highly doped regions formed at the face to be of the second conductivity type, the third and fourth highly doped regions spaced from the first

Abstract: A static random access memory timing scheme is disclosed in which the latching of a sense amplifier is derived from substantially the same point in the a timing chain as is the precharge/equalization signal, which is derived from the row address transition detection signal (as is the word line gating signal). Fan-in is minimized so as to allow good immunity to gamma dot and parameter variations.

Abstract: The present invention relates generally to single instruction, multiple data processors. More particularly, the invention relates to processors having a one dimensional array of processing elements, that finds particular application in digital signal processing such as Improved Definition Television (IDTV). Additionally, the invention relates to improvements to the processors, television and video systems and other systems improvements and methods of their operation and control.