Abstract: A patch antenna, which may be one element of an antenna array, is formed on one broad surface of a semiconductor plate. A ground plane is formed on the second broad surface. This semiconductor is doped in regions near a periphery of the patch to define a semiconductor PN junction have electrode contacts to the patch and to the ground plane. The junction has capacitance which tunes the patch antenna. The characteristics of the junction are controlled by bias to selectively tune the patch antenna. The bias is a direct voltage in one embodiment of the invention. In another embodiment, the junction work function itself provides a bias which is controlled by temperature control of the diode.