Abstract: A synthetic array processor wherein radar data, received from an area to be mapped during a plurality of subarray flight path segments, is electronically focused in parallel processing channels to form a series of approximately rectangularly shaped low azimuth resolution maps; and signals associated with corresponding portions of each low resolution map are further processed by means of digital filtering techniques to provide, in a format readily adapted for display, a high azimuth resolution map.

Abstract: The specification describes a process for growing selected compound semiconductors of high stoichiometry and purity and includes the steps of providing both a dynamic vacuum and a predetermined temperature profile in a container or tube containing a chosen semiconductor source material. The dynamic vacuum is used to create a predetermined minimum overpressure. P.sub.min, in this container with respect to the vapor pressure of the source material, while simultaneously removing impurities through in opening in the container during the crystal growth process. This process involves the vapor transport of elements of the selected compound semiconductor from the source material to a suitable support member, such as a graphite crucible which is maintained at a predetermined uniform controlled temperature.

Abstract: The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no postimplantation annealing.

Abstract: The specification describes an improved III-V compound solar cell structure and fabrication process therefor wherein a P-type layer of gallium aluminum arsenide is epitaxially grown on an N-type gallium arsenide substrate to form a P-type region and a PN junction in the substrate. Controlled amounts of beryllium are introduced into both the epitaxial layer and the substrate, either during epitaxial growth or by using beryllium ion implantation techniques subsequent to the P-type epitaxial growth step. The homojunction-heterostructure device thus formed exhibits improved power conversion efficiencies in excess of 17%.

Abstract: The specification describes a means and method for mixing millimeter wave RF energy of one chosen transverse electric (TE) waveguide mode with a local oscillator signal of another chosen TE waveguide mode, and such mixing is accomplished by applying those RF and local oscillator signals to a pair of reverse poled and parallel connected mixer diodes. These mixer diodes are connected at a chosen location within a rectangular waveguide and between top and bottom walls thereof and are symmetrically spaced across the width of the waveguide with respect to the center or a/2 location in the guide, with "a" being the width dimension in the guide. An IF output signal is derived at a common output node for the mixer diodes.

Abstract: The specification describes a novel pyroelectric detector in which one input detector electrode is mounted directly on one surface of a pyroelectric substrate and is used for absorbing chopped incoming infrared radiation. The output detector electrodes are capacitively coupled to the reverse substrate surface and provide an AC coupled output signal with a minimum of conductive heat transfer from the pyroelectric substrate.

Abstract: The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implanatation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region.

Abstract: The specification describes a solid state microwave power combiner wherein a plurality of solid state power generating devices are mounted between adjacent conical support and housing structures. These structures define the microwave electrical circuits for these devices, and also as provide a waveguiding region for propagating energy from these devices to a common output line. Both the support and housing structures have their apexes integrally joined, respectively, to input and output conductors of a common output coaxial line used for coupling power out of the combiner. This novel geometrical configuration minimizes the electrical distance between the power generating devices and the coaxial output line, maximizes the packing density of the structure and optimizes the electrical performance of RF termination elements for these devices.

Abstract: The specification describes a gallium aluminum arsenide-gallium arsenide-germanium solar cell and fabrication process therefor wherein the deposition of a layer of gallium aluminum arsenide establishes a first PN junction in the GaAs of one bandgap energy on one side of a gallium arsenide substrate, and the deposition of a layer of germanium establishes a second PN junction in Ge of a different bandgap energy on the other side of the GaAs substrate. The two PN junctions are responsive respectively to different wavelength ranges of solar energy to thus enhance the power output capability of a single wafer (substrate) solar cell. Utilization of the Group IV element germanium, as contrasted to compound semiconductors, simplifies the process control requirements relative to known prior art compound semiconductor processes, and germanium also provides a good crystal lattice match with gallium arsenide and thereby maximizes process yields.

Abstract: An electronic package including a single substrate for supporting a semiconductor device or die, an integrated circuit chip, or other electronic components on each side thereof. The substrate is configured with a plurality of cavities which are spaced around its outer periphery for receiving a corresponding plurality of electrical pin connections. These pin connections are readily accessible for connection to devices, circuits or other electrical components mounted on both sides of the substrate, thereby maximizing the packing density of the package.

Abstract: The specification describes an improved III-V compound solar cell structure and fabrication process therefor wherein a P-type layer of gallium aluminum arsenide is epitaxially grown on an N-type gallium arsenide substrate to form a P-type region and a PN junction in the substrate. Controlled amounts of beryllium are introduced into both the epitaxial layer and the substrate, either during epitaxial growth or by using beryllium ion implantation techniques subsequent to the P-type epitaxial growth step. The homojunction-heterostructure device thus formed exhibits improved power conversion efficiencies in excess of 17%.

Abstract: The specification describes a semiconductor solar cell and fabrication process therefor wherein a thin N-type gallium arsenide layer is deposited on a larger P-type substrate layer which is selected from the group of III-V ternary compounds consisting of aluminum phosphide antimonide, AlPSb, and aluminum indium phosphide, AlInP. P-type impurities are diffused from the substrate layer into a portion of the thin N-type gallium arsenide layer to form P-type region therein which defines a PN junction in the thin gallium arsenide layer. Thus, the quantity of gallium arsenide required to provide this PN photovoltaic junction layer in the cell is minimized, and the P-type substrate serves as a high bandgap window layer for the cell. Such high bandgap of this window material is especially well suited for efficiently transmitting the blue spectrum of sunlight to the PN junction, thus enhancing the power conversion efficiency of the solar cell.

Abstract: The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implantation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region.

Abstract: The specification describes a process for annealing electronic material, and particularly semiconductor crystals, wherein the material is submerged in a molten solution which contains the element or elements which comprise the material as solute. The solution is maintained at a temperature near the point at which the melt is saturated with solute. However, the material being annealed is physically isolated from actual contact with the solution by a gas-porous and liquid-tight container in a manner that exposes the material only to equilibriating gases from the molten solution during the annealing process. Thus, dissociation and decomposition of a semiconductor material during annealing is prevented by these equilibriating gases while using this extremely simple, unique and novel procedure which insures that no solid (other than the material holder) or liquid makes actual contact with the semiconductor material being annealed.

Abstract: The specification describes a gallium aluminum arsenide-gallium arsenide-germanium solar cell and fabrication process therefor wherein the deposition of a layer of gallium aluminum arsenide establishes a first PN junction in the GaAs of one bandgap energy on one side of a gallium arsenide substrate, and the deposition of a layer of germanium establishes a second PN junction in Ge of a different bandgap energy on the other side of the GaAs substrate. The two PN junctions are responsive respectively to different wavelength ranges of solar energy to thus enhance the power output capability of a single wafer (substrate) solar cell. Utilization of the Group IV element germanium, as contrasted to compound semiconductors, simplifies the process control requirements relative to known prior art compound semiconductor processes, and germanium also provides a good crystal lattice match with gallium arsenide and thereby maximizes process yields.

Abstract: The specification describes a process and apparatus for aligning a mask and semiconductor wafer during X-ray lithography which comprises, among other things, inserting a novel flexible spacer between the mask and wafer so as to maintain a vacuum seal between the mask and wafer. This spacer has a plurality of selectively spaced studs with flat surfaces adapted to receive the mask and wafer in intimate contact and conform to surface variations thereon. This spacer serves to maintain a substantially constant distance between mask and wafer over the entire facing surfaces of these two members during an X-ray lithographic process. A sealing member is disposed at the periphery of the flexible spacer and is also in intimate contact with the mask and wafer so as to maintain a vacuum seal between the mask and wafer. The facing surfaces of the mask and wafer will be forced against the studs on the spacer by atmospheric pressure so long as a vacuum is maintained in the sealed space between the mask and wafer.

Abstract: The specification describes a compound semiconductor solar cell and fabrication process therefor wherein both the P and N-type layers of the cell are polycrystalline semiconducting material and have large crystallites with grain boundaries of similar dimensions and spacings. These grain boundaries are spaced apart by a distance substantially greater than the optical absorption length, .LAMBDA., in one of the layers and by an amount sufficient to permit substantial numbers of photon-generated carriers in that one layer to cross the PN junction between the layers. Thus, substantial power is generated without the requirement for using expensive monocrystalline semiconductive materials.

Abstract: The specification describes a process for fabricating semiconductor devices and circuits in which lateral geometry dimensions determining the performance level of the device or circuit are extremely small. In this process electron beam microfabrication techniques are used to define these extremely small dimensions. The complete fabrication process uses standard photolithography for the definition of some of the device geometry and mask patterns, and partitioning of pattern definition between electron beam microfabrication and standard photolithography is utilized according to pattern resolution requirements, and is optimized for the highest yield-throughout product.

Abstract: A thin film solar cell having adjacent layers of P and N type polycrystalline semiconductor material which define a PN junction boundary, the improvement comprising a layer of n-type polycrystalline cadmium sulfide disposed on a chosen substrate material and having large grains with lateral grain boundaries on the order of about 20 micrometers or greater and a layer of polycrystalline P-type indium phosphide disposed on said layer of polycrystalline cadmium sulfide and having a thickness on the order of between 1.0 and 4.0 micrometers and further having large replicated grain boundaries with lateral dimensions and spacings approximately the same as the lateral dimensions and spacings of said large grains of cadmium sulfide, whereby the lateral grain dimensions in said cadmium sulfide and indium phosphide layers are maximized while the quantity of indium in said solar cell is minimized.

Abstract: The specification describes a semiconductor solar cell and fabrication process therefor wherein a thin N-type gallium arsenide layer is deposited on a larger P-type substrate layer which is selected from the group of III-V ternary compounds consisting of aluminum phosphide antimonide, AlPSb, and aluminum indium phosphide, AlInP. P-type impurities are diffused from the substrate layer into a portion of the thin N-type gallium arsenide layer to form P-type region therein which defines a PN junction in the thin gallium arsenide layer. Thus, the quantity of gallium arsenide required to provide this PN photovoltaic junction layer in the cell is minimized, and the P-type substrate serves as a high bandgap window layer for the cell. Such high bandgap of this window material is especially well suited for efficiently transmitting the blue spectrum of sunlight to the PN junction, thus enhancing the power conversion efficiency of the solar cell.