Abstract: A self-timed data amplifier and method for an integrated circuit memory device which overcomes the power consumption problems of conventional static data amplifiers while providing a high speed amplification function within design margins. By self-timing the un-equilibration of the data lines ("DQ" and its complement "DQB"), powering the main data amplifier and latching its output all with the same clock that controls the column address for the device, a high speed, low power, low risk approach is achieved. In a particular embodiment of the present invention, this may be effectuated by the integration of an amplifying, latching and equilibration function wherein all of the related circuitry is controlled by the memory device Y-clock signal (YCLKB) and the write signal (WRITEB) signal. In operation, the YCLKB signal goes "low" when a column address is determined to be valid, which then allows the DQ and DQB lines to be driven.

Abstract: A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level.

Abstract: A method for aggregating distributed information from a plurality of data sources each having an address. A plurality of user criteria are received and site specific information describing idiosyncrasies of each data source are stored. A plurality of query messages are generated based upon the received criteria and the stored idiosyncrasy information. For each query message, a communication packet is generated comprising the query message and an address for the corresponding data source. A plurality of communication ports are created with each port associated with one of the communication packets. Each communication packet is sent over its associated port to the addressed data source.

Abstract: A tilt compensation method, circuit and apparatus utilizes a two axis tilt sensor or two single axis tilt sensors for alerting, a user and/or compensating a surveying instrument for off vertical alignment above a reference point when the instrument support is free to move about the reference point, e.g., when mounted on a monopod support. The sensor comprises a cell having a central electrode and four peripheral electrodes spaced 90 degrees apart around the central electrode. Fluid in the cell chamber changes the conductance of the electrodes with reference to the central electrode. The cell is mounted to the support or to the instrument itself. A microprocessor preferably provides a square wave drive signal selectively to alternate pairs of the opposing electrodes through tristate buffers while at the same time the microprocessor provides a channel select signal to the gate of the tristate buffers to float the idle electrodes.

Abstract: A current sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory device which allows the amplifier's differential voltage level and speed to track that of the sense amplifier supplying the information, thereby achieving the needed margin for critical synchronous timing. The reliability of the differential amplifier is also increased due to the provision of a larger differential signal and higher supply voltage levels. In a preferred embodiment, an n-channel transistor serves as a regulator with its drain terminal coupled to an unregulated supply voltage source ("V.sub.cc "). The gate of the transistor is then coupled to a regulated supply voltage ("V.sub.ccp ") which is a function of the voltage supply for the sense amplifier. The source of the transistor is connected to the sources of the p-channel transistors in the main amplifier which provide feedback to the main amplifier.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: A process for providing a thin encapsulation layer for thin film heads includes controlling the bias voltage of the substrate and head during the encapsulation layer deposition process. The bias voltage is first maintained at approximately 60 volts while the standard encapsulation overcoat portion of the layer is deposited. This may take approximately one hour. Over the next thirty minutes, the bias voltage is ramped from approximately 60 volts to approximately 200 volts in a gradual, linear manner to reduce the stress on the wafer and heads. The bias voltage is then maintained at approximately 200 volts for the next three hours while the remainder of the encapsulation layer is deposited. Because of the higher bias voltage, the layer is deposited in a substantially planar manner so that there is no need for a lapping back process. Stress to the head is minimized by ramping the bias voltage. In addition, relatively short studs can be used for routing signals to and from the read/write elements of the head.

Abstract: In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper logic for expanding complex instructions into microinstructions. Control logic parses a bundle of instructions into sub-bundles of non-complex instructions and sub-bundles of microinstructions. The control logic detects when a complex instruction is present in a bundle of instructions and directs the complex instruction to the helper logic for expansion into two or more microinstructions. Each non-complex instruction bypasses the helper logic, thereby improving the execution performance of the non-complex instruction.

Abstract: A method of forming a top pole member in a magnetic recording head having a bottom pole member, an insulating layer on said bottom pole member, and a shared pole member over the bottom pole member on a ceramic substrate comprises the steps of depositing a ferromagnetic material on the shared pole portion forming a shared pole tip; depositing an insulating layer on and over the shared pole and the shared pole tip; mechanically forming a planar insulating layer surface over the shared pole member exposing the shared pole tip flush with said planar surface; recessing the pole tip below said planar surface; depositing a gap layer over the planar surface of the insulating layer and the recessed pole tip. This layer forms a channel over the recessed pole tip. The top pole member is then deposited into and over the channel over the recessed pole tip. The top pole tip thus formed is automatically centered and aligned with the shared pole tip without the necessity of ion beam milling.

Abstract: A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.

Abstract: In a modular tower building block system for containing computing system devices, an I/O bus is incorporated into the modular blocks of the building block system by using a printed circuit board to carry the I/O bus in each modular block. The printed circuit board is mounted and positioned in each modular block to electrically connect with a printed circuit board in a next adjacent modular block when two modular blocks are stacked on each other. Also, there are a plurality of I/O buses on the printed circuit boards and only one I/O bus is distributed from each modular block. The printed circuit board is precisely located in each modular block at a predetermined position. Alignment pins and receivers provide alignment between stacked modular blocks to precisely position one modular block to the other modular block. This also aligns electrical connectors on the printed circuit boards of the stacked blocks so that the connectors on the printed circuit boards from two blocks mate when the two blocks are stacked.

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array. In an alternative embodiment, the FIFO memory device includes a "Retransmit" feature which allows data to be read from the device multiple times as well as the Read Pointer to be selectively placed under user control.

Abstract: A closed loop wire saw loop, a method for making the closed wire saw loop, and an apparatus and method for slicing a work piece, in particular, a polysilicon or single crystal silicon ingot, utilizing a closed loop of diamond impregnated wire in which the work piece (or ingot) is rotated about its longitudinal axis as the diamond wire is driven orthogonally to it and advanced from a position adjoining the outer diameter ("OD") of the ingot towards its inner diameter ("ID"). In this manner, the diamond wire cuts through the work piece at a substantially tangential point to the circumference of the cut instead of through up to the entire diameter of the piece and single crystal silicon ingots of 300 mm to 400 mm or more may be sliced into wafers relatively quickly, with minimal `kerf` loss and less extensive follow-on lapping operations. The closed wire saw loop is made by squaring and welding the wire ends together and then twice heat treating the weld at about 1500 F.

Abstract: An apparatus and method for accurately determining a target distance in adverse weather conditions utilizing both LASER and RADAR is disclosed. The radar signals are used to determine an approximate range which is then used as a gating window for the determination of which laser reflection is from the actual target as opposed to a reflection from the atmospheric interference. The method basically comprises the steps of initiating a radar pulse in the direction of a target and receiving a reflection, transmitting a laser signal and receiving a plurality of reflections, determining an approximate range based on the radar signals, and using this approximate range to ascertain which of the laser reflections is from the target. This determination is preferably made by generating a gating signal and gate width from the radar signals and passing the set of laser range signals through the gate to eliminate the false signals and select the signal that survives the gate as the accurate target range.

Abstract: A high bandwidth central memory controller utilizing a pipelined TDM bus such that each serial interface can sustain a bandwidth of up to 100 MByte/second for both the transmission and reception of variable length frames. Each port is assigned a fixed number of queues, a TDM slot number and the address routing for all other queues associated with the remaining ports at initialization, such that when a frame is received, the appropriate queue is determined from the addressing in the frame header and the initialized route tables. When the port's TDM slot for a memory request is active, a request for the output queue is made to the central memory controller if an "output queue available" indication is returned and the frame data is placed on the bus during the input port's data TDM slot. If the output queue is not available, the input port may either discard the received data frame or generate a busy/reject frame to be placed on one of its own output queues during its TDM data slot.

Abstract: A highly precise range measurement instrument is made possible through the use of a novel and efficient precision timing circuit which makes use of the instrument's internal central processing unit crystal oscillator. A multi-point calibration function includes the determination of a "zero" value and a "cal" value through the addition of a known calibrated pulse width thereby providing the origin and scale for determining distance with the constant linear discharge of capacitor.

Abstract: A sensor for determining the position of a movable object along a selected axis. The system includes a target positioned at a location aligned with the selected axis. An optical energy emitter is mounted on the movable object and has a beam dispersion greater than two degrees directed at the target. An optical energy receiver is mounted on the movable object and aligned to receive optical energy reflected by the target. The optical energy detector generates a receive signal indicating reception of the optical energy. A time of flight circuit coupled to the emitter and receiver generates a flight time signal indicating the elapsed time from emission of the optical energy to reception of reflected optical energy. A control circuit monitors the flight time signal and outputs a position signal indicating position of the movable object with respect to the target.

Abstract: An apparatus and method for measuring coefficients of retroreflectance of retroreflective surfaces such as road signs involves use of a modified light based range finder. The apparatus includes a power attenuation factor data base which relates pulse width of received pulses to power attenuation of the transmitted pulses. The range finder calculates target range based on time of flight of light pulses. The apparatus automatically calculates the absolute coefficient of retroreflectance for an unknown reflective surface being measured by comparison of the measurement to a reading with the same instrument of a known reflectance standard.

Abstract: In a processor executing instructions speculatively or out-of-order, an apparatus for tracking traps, exceptions, and interrupts within the processor. A table stores front-end and back-end traps associated with an instruction, and an instruction retirement module retires the instructions in order if no traps were associated with older instructions in the processor. In this way, the proper trap sequence of events is maintained so that traps can be properly handled.

Abstract: A receiver circuit for an integrated circuit including an input buffer having an input coupled to receive an external input signal and an output coupled to generate a buffered input signal in response to the external input signal. The input buffer is selectively enabled by a control signal. A latch is coupled to receive the buffered input signal and to generate a latched output signal. A delay circuit is coupled to receive the latched output signal and to generate a delayed signal. A comparator is coupled to receive both the latched output signal and the delayed signal. The comparator has an output coupled to the input buffer to generate the control signal.