Abstract: A technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable elements wherein each group of replaceable elements contains a circuit which enables an element group within a chained set to determine whether it is the "leftmost" (or first) element used within the set by monitoring the state of an adjacent node. The node will transition to a logic "low" level if (and only if) a fuse within the set, (and located to the left of the node) is "blown" (or opened). By then multiplexing signals to select one or more elements within the first group and additional signals to select one or more elements within the second group, the necessary determination can be made to disable any given pair of elements based on the state of the fuses, the adjacent nodes and the additional signals.

Abstract: A word line boost-on-writes technique for a dynamic random access memory device in which the word lines are initially boosted upon opening of a page in the memory array and then again following each write command, or following a predetermined number of write cycles in the case of a burst write, in order that the precharge cycle can proceed without delay due to the boost operation. Each boost is applied for a limited duration so that the overall precharge time is not affected.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.

Abstract: An architecture for a serial ferroelectric memory device that incorporates the provision of a latch intermediate the device memory array and column decoder of a width equal to a row in the array. In operation, the presence of the latch ensures that each write access to the memory device loads a row into the latch. Data is then modified while retained in the latch and written back to the memory array at the end of the cycle. A read operation can perform a write-back from the latch to the memory array at the beginning of the cycle after data is loaded into the latch. The addition of the latch intermediate the column decoder and the memory array then serves to ensure that for typical block read operations each column of the memory array will experience the same single write back cycle. As a consequence, data retention reliability for the memory device is improved by mitigating the effects of disparate imprint on the memory cells of the memory array.

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: A data processor incorporating a memory array which is selectably configurable as either read/write or read only memory or the combination of both read/write and read only memory includes a memory mapper for receiving logical addresses from an arithmetic logic unit ("ALU") and converting the same to physical addresses within the memory array in accordance with configuration instructions stored in a local non-volatile memory. By utilizing a common memory technology for the memory array, such as non-volatile ferroelectric random access memory ("FRAM"), the proportions and layout of the memory array which may be utilized for MPU instructions and data may be selectably controlled. The use of a memory mapper also allows for the establishment of an effective password or encryption protection function for the memory array data of particular utility in conjunction with radio frequency identification ("RF/ID") transponders and other applications which must store sensitive data in non-volatile storage.

Abstract: Data is recovered despite a single point of failure in a data exchanging system while accommodating scaleable data transfer rate performance. In the environment of at least two disk array controllers, a serial dumping scheme assists in recovery of data from a fast memory. It is imperative to avoid loss of write data from a host computer which is received and acknowledged but not yet stored in a disk medium. The configuration ensures that at least one of the controllers will handle the data so as to correct single failure point errors and properly store that data on one of the disks of an array. A fast memory providing a buffer between a remote host computer and arrays of data storage media is managed so that data received for writing is duplicated for reliability of storage while data for reading to the host computer is manipulated with an enhanced bandwidth of fast memory operation.

Abstract: A method and apparatus for delaying frames received asynchronously from a fiber channel port until receive memory is properly sequenced for storing the delayed frames in which a circular buffer is positioned on the data path between the fiber channel port and the receive memory for delaying the frames in accordance with control signals generated by a sequencer having knowledge of the receive memory sequence count.

Abstract: An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.

Abstract: A method and apparatus for configuring a system that includes a plurality of interconnected components that each supports service parameters for communicating with other components in the system. A determination is made as to which components support service parameters that are compatible, and groups of components having compatible service parameters are identified. Adjacent components exchange information frames that identify their service parameters. Each component compares its service parameters with those of its adjacent components to determine whether they are compatible, updating its own service parameters if necessary. Any component that updates its service parameters issues another information frame. Thus, information frames are exchanged until it is determined which components support compatible service parameters, and what service parameters are to be used for communicating among those components. Additionally, a unique address is automatically assigned to every port in the system.

Abstract: A highly precise range measurement instrument is made possible through the use of a novel and efficient precision timing circuit which makes use of the instrument's internal central processing unit crystal oscillator. A multi-point calibration function includes the determination of a "zero" value and a "cal" value through the addition of a known calibrated pulse width thereby providing the origin and scale for determining distance with the constant linear discharge of capacitor.