Abstract: A system and method for supporting sequential burst counts of particular utility with respect to double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) devices wherein each memory bank is divided into halves, corresponding to Even (AOc=0) and Odd (AOc=1) portions. Separate address busses may be provided for those bits necessary to accommodate the maximum burst length. As the column addresses are loaded, the buffers associated with the Even bus check to determine if the pad address “Y” or “Y+1” should be loaded. Loading “Y+1” is necessary to support sequential counting if the start address is Odd (AOc=1). “Y” selects in the Odd and Even banks are then selected and incremented, concurrently. Nevertheless, the Even field is always “Y+1”, that is, YEven=YOdd+1.