Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain mutliple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration.

Abstract: A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices.

Abstract: A memory organization for holding memory refresh data for a display uses input address selectors for memory modules for a segmented display to provide horizontal rotation of all data in the memory modules. On writing of vertical vectors, a logic tree using Exclusive ORs modifies memory address bits to provide tilt to the vertical vector and cause it to be orthogonal to horizontal vectors. Output data selectors read data from the memory modules to the display and derotate the data so that the display is restored to its original form.

Abstract: The bit configurations are arranged in M-bit code words, each word comprising a number D of data bits and an even number N of error correcting bits. The data bits are partitioned into N fields with an error correcting bit associated with each field to indicate the parity of the associated field. The assignment of data bits to the N fields in such that, when the N fields are used to generate an N-bit error syndrome, this syndrome will contain an odd number n1 of bits at a first value if there is a single bit in error, where N-n1=n2 is also odd, and an even number of bits different from N to indicate a two-bit error. The number of bits of the first value are then used to determine whether the codeword is in its true or inverted form.

Abstract: A bias magnet for a bubble memory device is comprised of a single material low permeability magnet contoured to enhance the magnetic field in the central area of the magnet and is adapted to be slightly larger than the bubble memory chip and in thermal contact therewith, the entire bubble memory chip and bias magnet structure to be surrounded by the rotating magnetic field drive coil structure.

Abstract: Pseudo-random numbers (PRNs) have great importance in data processing and encryption. The standard technique for generating PRNs on computers at the present time involves software implementation of recursively computing PRN.sub.n+1 =(PRN.sub.n)(b) mod M, in real number field which means that a relatively slow and involved multiplication must occur for each PRN, and each PRN calculation is strictly subsequent to previous PRM calculations. This disclosure shows a systolic multiplier implemented by a series of exclusive OR operations which generates simultaneously a new set of the PRN's from the current set of PRN's in parallel. The operation of multiplication mod M is performed over a finite field instead of a real number field. To facilitate the multiplication, the input operands are first transformed into a different representation that consists of more bits than that of the original ones. The operation of multiplication is then carried out in this transformed representation.

Abstract: An optical recording system has a system optical apparatus carried by a fine tracking system which moves the optical apparatus for small track seeking movements and for track following. The fine tracking system is carried by a linear actuator coarse tracking system which makes large track seeking movements so that the entire area of the optical recording media is available to the system. Both the coarse tracking system and the fine tracking system are operated by servo control loops. The fine tracking system responds to tracking status signals with respect to track following and track seeking signals in response to track addressing information. The coarse tracking system responds to position sensor signals derived from a position sensor which is associated with the fine tracking system and provides signals related to the relative position of the fine tracking system to the coarse tracking system.

Abstract: A digital storage includes several sections having different time characteristics. Such sections are operated in the overlap mode and include a common address and control circuit. The fast sections store data which are accessed more frequently or which are addressed first when data blocks are transferred. The digital storage may be used in a storage hierarchy comprising a cache storage and wherein only data blocks positioned at main storage address boundaries are transferred to the cache storage.

Abstract: A magnetic read head has a first embodiment comprising an elongated magnetoresistive element having a central region and distant ends. The central region has equipotential strips disposed intermediate to its ends, and detection circuitry is electrically connected to these intermediate equipotential strips to sense the changing resistance of the central region in the presence of data magnetically recorded on a medium. In a second embodiment, the magnetoresistive element is folded into a picture frame shape and has its ends joined. The element is vertically arranged so that one of the legs of the element is positioned in proximity to a selected track of a recording medium. A pair of equipotential strips are disposed at opposite ends of the leg to define a sensing region therebetween. Detection circuitry is connected to these equipotential strips to detect the changing resistance of the sensing region in the presence of the magnetic fields of the medium.

Abstract: In a first searching mode of the control program for the microprocessor, the microprocessor starts with a selected clock input and associated delay circuit and sets the delay circuit to an initial clocking point which is intermediate to the minimum and maximum delay points. The microprocessor then, at each pass of the control program, successively increments the delay period interposed by the delay circuit to cause the clock pulse to arrive later and later in time at the clock input until the associated circuit fails, to indicate the late clocking failure limit. In the second searching mode of the microprocessor control program, the microprocessor starts at the late clocking failure limit and at each subsequent pass of the program successively decrements the delay period interposed by the delay circuit to cause the clock signal to arrive earlier and earlier in time until the semiconductor device fails again, to indicate the early clocking failure limit.

Abstract: A magnetic read head has a first embodiment comprising an elongated magnetoresistive element having a central region and distant ends. The central region has equipotential strips disposed intermediate to its ends, and detection circuitry is electrically connected to these intermediate equipotential strips to sense the changing resistance of the central region in the presence of data magnetically recorded on a medium. In a second embodiment, the magnetoresistive element is folded into a picture frame shape and has its ends joined. The element is vertically arranged so that one of the legs of the element is positioned in proximity to a selected track of a recording medium. A pair of equipotential strips are disposed at opposite ends of the leg to define a sensing region therebetween. Detection circuitry is connected to these equipotential strips to detect the changing resistance of the sensing region in the presence of the magnetic fields of the medium.

Abstract: In a bubble memory package, a contoured, shaped magnet and filler plate combination is provided to shape the magnetic field in a uniform fashion to prevent the loss of magnetic flux density which normally tends to occur in the center of the magnet area of a planar, uniformly thick magnet.

Abstract: A hardware network or system is disclosed for testing LSI and VLSI logic device design and system design by simulation utilizing individual gate functions. The simulator system uses switching logic, random access memory, and a state table device to simulate particular test routines to test device design with functions which may appear in random or semi-random sequence.

Abstract: A process for producing high precision apertures in plastic components comprises the steps of: injection molding the component from a crystalline or semicrystalline thermoplastic material wherein at least one aperture is formed in the component during the molding step; inserting an annealing rod having an oversized diameter with respect to the aperture into the aperture; placing the component, with the annealing rod inserted into the aperture, into an oven at an elevated temperature for a period of time; allowing the component to cool; and withdrawing the annealing rod from the aperture of the component.

Abstract: A microcode control memory having a first memory for receiving initial instructions is shown in combination with at least one additional memory for executing multistep control functions in a computer system. The first memory receives all initial control instructions from an instruction stack and produces the appropriate control output. Simultaneously as part of the initial instruction, a memory select network receives a control bit so that an output select network connected to the output of all memories passes the output from the first memory to the output register. Single step instructions are processed continuously this way. Multistep instructions are performed by using a portion of the output from the first memory to serve as the address selection in one of the other memories. When a multistep instruction is completed, the output select network again selects the output from the first memory for gating to the output register.

Abstract: A focus initialization system is provided for optical data recording of the type in which an objective lens relatively near to the optical recording media is moved back and forth in comparatively small excursions to maintain focus for the read beam and write beam on the media. This system initializes or loads a conventional focusing system by starting the objective lens at a position at the far end of its travel limit, preferably, with the objective lens furthest from the optical media. The objective lens moves slowly towards the optical media while the system operates to detect when a near focus condition exists. Known focusing detection systems produce a bipolar output voltage having a peak on either side of the exact focus point when a near to focus condition is achieved. The present system detects when the objective lens is at a near to focus condition in the range between bipolar voltage peaks on either side of the focused point.

Abstract: Focus sensing using a light detector array is accomplished in an optical recording system using the light beam returned from the recording media through the objective focusing lens by passing the beam through a spherical focusing lens using a mask such as a knife edge which only passes a portion of the beam to the light detector array. The light detector array is matched to the mask and detects the different partial image patterns formed as a result of the close to focus condition with the recording media too far away from the objective lens and the near to focus condition with the media too close to the objective lens. In the focused condition, the light detector array receives a comparatively fine focused spot of light. Alternative embodiments of the present invention may use a cylindrical lens which in the focused condition creates a longitudinal bar of light.

Abstract: A network access device (NAD) is comprised of a data set for coupling to a data communication trunk, a trunk control unit (TCU) connected with the data set, a trunk control interface (TCI) connecting the TCU to an internal data bus, an internal memory, a microprocessor control and a device interface for connection to a computer or some computer peripheral device. The data set provides for two-way communication from the data trunk to the TCU. Various network access devices connected to the data trunk communicate with one another. Every normal communication between NADs includes a concurrent, predictable state change in both NADs. The response to a message from one NAD to another includes information concerning what occurred upon receipt of the message. Various latches, sequencers, microprocessor logic and registers provide for functions according to various input and output states of response.

Abstract: A magnetic tester for hubs employed in disk-memory cartridges is provided to measure the mounting strength of hub armatures, the gross magnetic hub-retaining force, the hub-diaphragm preload strength, the net hub-retaining force, the variation of hub preload with diaphragm deflection, and the variation of hub-retaining force with magnetomotive force.

Abstract: A large-scale integrated circuit (LSI) chip has an individual voltage level sensing circuit connected with each input and output connecting pin so that isolation between the pins is maintained and so that the individual level sensor output can provide an indication of an abnormal voltage on the input/output pin. The outputs of all level sensors for all input and output pins is connected in common to the input of a comparator circuit. The comparator circuit has a fault detection threshold voltage input and provides a fault indication output signal whenever the voltage input from the level sensor circuits is outside of the detection threshold voltage range. A number of logic chips will have particular input/output pins connected together in a circuit in conventional applications. An open circuit anywhere in the interconnected network will cause some number of input/output pins dependent on the fault location to be pulled out of the detection threshold voltage range.