Abstract: A logic circuit for implementing a flip-flop circuit that operates stably and at high speed at a low supply voltage of about 1 V. The logic circuit includes transistors 25,26,31 for forming a first current mirror circuit 2; transistors 27,28 for converting clock signals to current signals; transistors 19,22,23 for forming a second current mirror circuit 3; and transistors 20,21,24 forming a third current mirror circuit 4. These current mirror circuits supply a current nearly equal to the current from transistors 27,28 to the circuits connected respectively to those current mirror circuits. Transistors 29,30, current source 47, voltage source 50 and voltage comparison circuit 51 form a voltage maintenance circuit. Transistors 11,12 and resistors 41,42 form an input stage of a master D flip-flop D-FF, and transistors 13,14 form the signal-holding row of the master D flip-flop D-FF.