Abstract: A current generation, quad RAS, single CAS, stacked component (101) including four 4 Mb×4 bits 11/11 DRAMs (210-213) is arranged to emulate a next generation 16 Mb×4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller (105) includes a row address of 12 bits and a column address of 12 bits. Each DRAM (210-213) within the current generation DRAM component (101) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic (103). The additional row address bit is decoded by the decoding logic (103) to direct the RAS signals over two of the four RAS lines (201-204), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic (103) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line (205) directs the CAS signal to all of the stacked DRAMs (210-213).

Abstract: A method and apparatus of interconnecting with a system board is presented. A system board having a metal stiffener mounted thereon is provided with an opening in the stiffener to provide access to an area of interest on the system board. A probe test assembly is positioned at the opening and secured to the stiffener when testing is desired to provide access to the pins of the device under test (e.g., a Multi Chip Module (MCM) on the system board). Alternatively, a system enhancement device, such as a MCM or Single Chip Module (SCM) having additional Central Processing Units (CPU's) or other features, may be installed on the system board at the opening in the stiffener to enhance the function of the system board. Another alternate includes an interface assembly positioned at the opening in the stiffener. A cover is positioned at the opening and secured to the stiffener at all other times.