Abstract: A data input circuit for a semiconductor memory device uses an echo clock generator to reduce the clock cycle time. The echo clock is transmitted in the memory device with the data, thereby reducing the effects of clock skew and increasing the overall device operation speed. The circuit is particularly applicable to double data rate synchronous DRAM (DDR-SDRAM) circuitry.

Abstract: An internal power control circuit for a semiconductor device allows easy testing of the internal circuit blocks or memory arrays at various voltage levels. In the semiconductor device, internal voltage switching circuits connected between the internal power supply line and each array power supply line are switched ON or OFF according to signals applied to control pads coupled to each internal voltage switching circuit. During normal operation, a power voltage generated by the internal voltage generator is applied through an internal power supply line to each array power supply line coupled to the internal circuit blocks. During a test operation, different power voltages may be applied to the control pads to selectively decouple individual array power supply lines from the internal power supply line, and selectively couple the power voltages applied to the control pads to the corresponding array power supply lines and internal circuit blocks.

Abstract: A BiDMOS device in which a bipolar transistor and a DMOS transistor are formed on the same substrate, thereby resulting in a high degree of integration, and a method of fabricating the same using a reduced number of process steps. A high voltage operating characteristic is achieved because the gate of the DMOS transistor isolates the base and collector of the bipolar transistor. In addition, the junction capacitance between the bipolar base and collector regions is considerably reduced due to the isolation provided by the DMOS gate polysilicon.

Abstract: A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.

Abstract: A universal burn-in board for burning-in semiconductor devices. The universal burn-in board is easily reconfigurable so that it may be used with a variety of semiconductor devices having the same pin configuration but different functional characteristics.

Abstract: The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line.

Abstract: A column decoder for a semiconductor memory device capable of a high-speed data access, such as in a synchronous memory. The column decoder receives and decodes a column address signal and produces a column select signal for driving a corresponding column select gate in accordance with the result of decoding. The column decoder includes a pre-decoder composed of a first pre-decoding section for pre-decoding the column address signal and producing at least one asynchronous pre-decoded signal, and a second pre-decoding section for pre-decoding the column address signal in response to a clock signal and producing at least one synchronous pre-decoded signal and enable signal; and a main decoder for producing at least one column select signal which is activated in response to the enable signal and is de-activated in response to a combination of the synchronous and asynchronous pre-decoded signals.

Abstract: A semiconductor memory device in which word lines are arranged so as to improve the yield with respect to bridging defects. The semiconductor memory device of the present invention has a plurality of interconnects arranged in parallel on a cell array portion, in which the interconnects are comprised of power lines and ground lines arranged alternately on the cell array portion, main word lines arranged on each side of the power lines, and a plurality of block word lines sequentially arranged between a single main word line and a ground line adjacent thereto and controlled by the main word line. In this way, interconnects are arranged in alternating groups so that interconnects having the same logic level during the standby mode are grouped together. The result of this arrangement is that interconnect bridges within a group will not lead to increased standby current, thereby substantially improving the yield of the semiconductor memory device.

Abstract: A method for manufacturing a three-dimensionally structured vertical transistor or memory cell including the steps of forming a silicon-on-insulator (SOI) structure on a semiconductor substrate, sequentially depositing a drain region, a channel region and a source region on the SOI substrate structure, a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, to thereby increase the integration of a device. This process and structure avoids the characteristic degradation caused by the leakage current associated with the trench process and structure.

Abstract: A thin film transistor formed in a liquid crystal display, comprising; a silicon layer formed over a transparent substrate, a first insulating layer formed over the silicon layer, a gate electrode and a plurality of gate line electrodes formed on the first insulating layer, a second insulating layer formed over the gate electrode and the gate line electrodes having a plurality of contact holes, and a metal line ohmically connected to the gate electrode and the plurality of gate line electrodes through the plurality of contact holes.

Abstract: A method of forming metal lines such as titanium and aluminum on a semiconductor wafer by sputtering at a high temperature, preferably in the range of approximately 500.degree. C. to 800.degree. C. This method decreases the contact resistance between the layers while reducing the number of processing steps.

Abstract: A method of manufacturing thin film transistors for use in a liquid crystal display which reduces the failures due to excessive leakage current. A silicon layer, first insulating layer, and gate electrode layer are serially formed over a transparent substrate. The gate electrode layer is patterned to form a plurality of gate electrodes and associated pairs of gate line electrodes, and the silicon layer is patterned into thin-film transistor regions. Then, a relatively thick second insulating layer is formed over the substrate, and contact holes are formed in the second insulating layer. Finally, a metal layer is formed and patterned over the second insulating layer and through the contact holes to connect each gate electrode with its associated pair of gate line electrodes; and to form source and drain electrodes.

Abstract: A vacuum sputtering apparatus for forming metal lines on a semiconductor wafer, including an annular reactive gas injector and a silicon carbide chuck for direct uniform heating of the wafer to a high temperature, preferably in the range of approximately 500.degree. C. to 800.degree. C., thereby allowing the deposition of titanium and titanium nitride layers having uniform thickness and composition.

Abstract: A synchronous random access memory device having an external address mode of operation and a burst mode of operation, in which a counter control circuit resets a burst mode counter during the external address mode of operation.

Abstract: A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.