Abstract: A method is disclosed for selectively overlaying portions of a default firmware code for a microcontroller of an FPGA interface device. The FPGA interface device includes a microcontroller, an on-board FPGA, and a memory having first and second pages. Upon initial power-up of the interface device, the default firmware code is loaded into the first memory page. Thereafter, the microcontroller executes instructions received from a host system using the firmware code loaded in the first memory page. Where it is desired to update or modify the firmware code, an overlay code is stored in the second memory page. The overlay code corresponds to selected portions of the default firmware code. Overlay flags are asserted for each of the selected portions of the default firmware code for which a corresponding overlay code is loaded in the second memory page.

Abstract: A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

Abstract: A CAM device having a plurality of CAM blocks is partitioned into a number of individually searchable partitions, where each partition may include one or more CAM blocks of the CAM device. In one embodiment, each CAM block is connected to a block select circuit that stores a class code indicating what class or type of data is stored in the block. The same class code may be stored in any number of block select circuits to define a partition as including the corresponding number of CAM blocks. During compare operations between a comparand word and data stored in the CAM device, a search code is provided to the block select circuits. Each block select circuit compares the search code with its class code and, in response thereto, selectively enables or disables the corresponding CAM block for the compare operation.

Abstract: A method is disclosed for reconfiguring an on-board FPGA of an interface device without resetting the interface device. The FPGA interface device also includes a microcontroller, and the on-board FPGA has a serial data port coupled to a first, non-volatile memory and a parallel data port coupled to a second memory, which may be a volatile memory. The default configuration design is stored in the non-volatile memory. The on-board FPGA is initially in a serial configuration mode such that upon power-up, the on-board FPGA looks to the first memory via its serial port for the configuration design. Where it is desired to reconfigure the on-board FPGA, a new configuration design is stored in the second memory, and the on-board FPGA is instructed to reconfigure itself in parallel mode. In response thereto, the on-board FPGA looks to the second memory via its parallel port, retrieves the new configuration design, and then reconfigures itself accordingly.

Abstract: A method is disclosed for alerting a user of a low power condition on, for instance, an FPGA interface device. An interface device having a microcontroller and an associated power plane for powering the microcontroller and other component on the interface device includes a detection circuit coupled to monitor the voltage level of the associated power plane. When the voltage level of the voltage plane falls below a predetermined threshold voltage, the detection circuit sends a low power flag to a host system. The low power flag, which is preferably sent to the host system using a USB port connection, alerts the host system of the low power condition on the interface device. The predetermined threshold voltage is selected to be a suitable amount higher than the minimum operating voltage for the microcontroller so as to allow sufficient time for the microcontroller to send the low power flag to the host system.

Abstract: The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame register for loading configuration data into the FPGA. When a portion of the FPGA is to be reconfigured, data are loaded by a portion of the FPGA not being reconfigured into the frame register of the FPGA and addressed to the portion of the FPGA being reconfigured. Loading of the data is accomplished by forming a configuration data stream in the portion of the FPGA not being reconfigured, then applying the configuration data stream to an output buffer of the FPGA and forwarding that data to an input buffer that is connected to a frame register of the FPGA configuration structure.

Abstract: The present invention provides an apparatus for converting logic signals of a first voltage level to logic signals of a second voltage level in response to a control signal indicative of whether logic signals on an associated target device are of the first or second voltage level. An output configuration includes a de-multiplexer having an input terminal coupled to receive an output signal of an associated logic circuit, a control terminal coupled to receive a control signal, and first and second output terminals, the first de-multiplexer output terminal being connected to the target device. A switch coupled between the second de-multiplexer output terminal and the target device has a control terminal coupled to receive the control signal. When the control signal is in a first state, a voltage drop across the switch converts the logic signals of the first voltage level to logic signals of the second voltage level.