Abstract: An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA. The fingerprint is used as a key for an encryption system that protects against illegal use and/or copying of configuration data. In some embodiments, the propagation delay of various circuit elements formed on the FPGA are used to generate the fingerprint. In one embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In some embodiments, a ratio of measurable values may be used to generate the fingerprint. In other embodiments, differences in transistor threshold voltages are used to generate the fingerprint. In still other embodiments, variations in line widths are used to generate the fingerprint.

Abstract: An IC package includes an IC die mounted on a substrate that includes an ESD protection structure formed within the substrate to dissipate any charge accumulation associated with the package's no-connect pins resulting from human body model ESD and/or voltage spikes during package testing. For some embodiments, the ESD protection structure includes a resistive element formed in the substrate between the no-connect pin and a power plane. For other embodiments, the ESD protection structure includes a conductive ring formed in the substrate and laterally surrounding the land pad of the no-connect pin.

Abstract: An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.

Abstract: A circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) is dynamically specified by providing a single code set embodying an expanded netlist representative of a dynamic circuit configuration of the pipeline core. The code set, which includes one or more parameter variables that determine the length and width of the implemented pipeline core, is synthesized by setting the parameter variables to selected constant values to generate a reduced netlist embodying a static circuit configuration for the implemented pipeline core.

Abstract: A method and apparatus is provided for a configurable input/output (I/O) interface within an integrated circuit to support a plurality of I/O standards. The configurable I/O interface exhibits a default operation that facilitates hot-swappability, which eliminates current paths within the I/O interface that may be created during plug-and-play operation of the I/O interface. The current paths are eliminated within the I/O interface even while the I/O interface is not receiving operational power, or while the I/O interface is in a power-on reset condition. A programmable option of the configurable I/O interface, on the other hand, alleviates over-voltage conditions while the I/O interface is tri-stated by activating shunt circuitry to conduct a clamp current during the over-voltage condition. The over-voltage condition is further alleviated by passively establishing current paths through existing circuitry within the I/O interface for the duration of the over-voltage condition.

Abstract: A method estimates the effective switched capacitance for any number of resource types that may be used to form a yet-to-be fabricated IC device using pre-layout netlists of the various resource types. The effective switched capacitances of the resource types are then combined with the operating frequency and the resource utilization of a user design to estimate the power consumption of the user design to be implemented in the device before physical samples of the device are available.

Abstract: An external storage device may transmit encrypted configuration data to a PLD during a configuration operation without transmitting the encryption key to the PLD and without retaining decryption information in the PLD. During a set-up operation, the encryption key is provided to the PLD, which generates an ID code upon power-up. The PLD generates a correction word in response to the encryption key and the ID code. The correction word is output from the PLD, which is powered-down, and is stored with the encrypted configuration data in the storage device. Then, during a configuration operation, the PLD is powered-on and re-generates the ID code. The correction word and the encrypted configuration data are transmitted to the PLD, which generates a decryption key in response to the re-generated ID code and the correction word.

Abstract: Individual storage locations in a PROM that stores a configuration file for a PLD may be directly addressed so that selected portions of the data stored therein may be replaced or updated with new data without having to erase all the contents of the PROM, reprogram the PROM with a new configuration file, and/or reconfigure the FPGA with the new configuration file. For some embodiments, a PROM includes a JTAG-compatible interface that is coupled to a JTAG-compatible test circuit provided within the PLD, and circuit within the PLD is configured to directly address individual storage locations in the PROM via the PROM's JTAG interface using well-known JTAG commands.

Abstract: A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to implement a circuit design embodied by the configuration data. The first die is electrically connected to the second die, and both the first die and second die are stacked and encapsulated together to form the packaged PLD solution. The configuration data is programmed into the masked-ROM by a manufacturer of both the masked-ROM and the PLD.

Abstract: A semiconductor package having a substrate and a die includes a plurality of conductive posts attached to the substrate and bonded to an active surface of the die via a plurality of corresponding microbumps. The conductive posts are flexible and extend beyond the top surface of the substrate a sufficient distance to absorb lateral forces exerted upon the microbumps.

Abstract: An output circuit allows the slew rate of its output signal to be selectively adjusted. The output driver circuit includes an output driver and pre-driver circuits. The output driver includes an output transistor coupled between a first supply voltage and the output terminal. The pre-driver circuit selectively adjusts a series resistance between the output transistor's gate and a second supply voltage in response to mode control signals.

Abstract: A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Abstract: A PLD (700) includes a plurality of logic blocks (701), a plurality of high gating circuits (702) coupled between corresponding logic blocks (701) and a supply voltage (VDD), a plurality of low gating circuits (703) coupled between corresponding logic blocks (701) and ground potential, and a plurality of control circuits (704) to provide control signals (CTRL) to the gating circuits. Each gating circuit pair selectively reduces the operating voltage provided to a corresponding logic block by one or more diode voltage drops in response to the corresponding control signal, thereby allowing the operating voltage provided to each logic block to be dynamically adjusted during run time in response to the control signals.

Abstract: An integrated circuit device such as a PLD is divided into a plurality of logic blocks, each including one or more resources of the device. The device includes a plurality of switch elements and a number of signal isolation circuits. The switch elements selectively disable corresponding logic blocks to reduce power consumption, and the signal isolation circuits selectively isolates corresponding logic blocks to prevent the transmission of invalid data from disabled logic blocks to enabled logic blocks.

Abstract: A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

Abstract: An oscillator circuit includes an enable circuit to generate an initialization signal and includes a ring oscillator responsive to the initialization signal and having a plurality of synchronous elements connected in a loop, wherein each synchronous element comprises a synchronous input terminal, a clock terminal, a first asynchronous input terminal, and an output terminal coupled to the clock terminal of a next synchronous element and coupled to the first asynchronous input terminal of a previous synchronous element. The enable circuit is independent of a delay path of the ring oscillator, and the ring oscillator generates a test clock signal having a period that does not include any signal delays associated with the enable circuit.

Abstract: A counter-controlled delay line includes a main oscillator for delaying edges of an input signal to generate a main clock signal. The main oscillator includes a plurality of gated delay elements connected in a ring. Each gated delay element includes a first control terminal to receive a corresponding load signal, and includes a second control terminal to receive a release signal. The release signal may simultaneously enable and disable state transitions in all delay elements, and the load signals may simultaneously drive an output of each delay element to any selected logic state.

Abstract: A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

Abstract: A method and apparatus compensate for process variations in the fabrication of semiconductor devices. A semiconductor device includes a control circuit that measures a performance parameter of the device, and in response thereto selectively biases one or more well regions of the device to compensate for process variations. For some embodiments, if measurement of the performance parameter indicates that the device does not fall within a specified range of operating parameters, the control circuit biases selected well regions to sufficiently alter the operating characteristics of transistors formed therein so that the device falls within the specified range of operating parameters.

Abstract: A method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In various embodiments, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.