Abstract: An FPGA includes a configuration control circuit having an internal memory that stores default configuration data which may configure the some or all of FPGA's logic blocks into a default state. A compressed bitstream includes one or more frame control bits indicative of whether corresponding configuration data is included in the bitstream. During configuration of the FPGA, the compressed bitstream is provided to the configuration control circuit from the external memory. As each frame control bit is received, its logic state is determined. If the frame control bit indicates that corresponding configuration data is included in the bitstream, the corresponding configuration data is read from the bitstream into a frame register. If, on the other hand, the frame control bit indicates that corresponding configuration data is not in the bitstream, default configuration data is read from the internal memory into the frame register.